Transcription of Introduction to Verilog HDL
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Introduction to Verilog HDL
Synopsys University Courseware Copyright 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez Introduction to Verilog HDL Jorge Ram rez Corp Application Engineer Synopsys University Courseware Copyright 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez Outline HDL Verilog Synthesis Verilog tutorial Synthesis coding guidelines Verilog - Test bench Fine State Machines References Lexical elements Data type representation Structures and Hierarchy Operators Assignments Control statements Task and functions Generate blocks Synopsys University Courseware Copyright 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez HDL Verilog Synopsys University Courseware Copyright 2011 Synopsys, Inc. All rights reserved. Developed by: Jorge Ramirez What is HDL?
Verilog •Verilog was developed by Gateway Design Automation as a proprietary language for logic simulation in 1984. •Gateway was acquired by Cadence in 1989 •Verilog was made an open standard in 1990 under the control of Open Verilog International. •The language became an IEEE standard in 1995 (IEEE STD 1364) and was updated in 2001 and
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