Transcription of JESD204B Overview - TI.com
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JESD204B Overview - TI.com
JESD204B Overview Texas Instruments High Speed Data Converter Training Outline JESD204B Standard at a Glance Benefits / Cost Timing Signals Layers Overview (Transport, Link, Physical) Deterministic Latency Subclasses JESD204B Standard at a Glance A standardized serial interface between data converters (ADCs and DACs) and logic devices (FPGAs or ASICs) Serial data rates up to Gbps Mechanism to achieve deterministic latency across the serial link Uses 8b/10b encoding for SerDes synchronization, clock recovery and DC balance JESD204B is a must for high density systems! TI Information NDA Required Feature JESD204 JESD204A JESD204B Introduction of Standard 2006 2008 2011 Maximum Lane Rate Gbps Gbps Gbps Multiple Lane Support No Yes Yes Multi-Lane Synchronization No Yes Yes Multi-Device Synchronization No Yes Yes Deterministic Latency No No Yes Harmonic Clocking No No Yes JESD204B Standard at a Glance JESD204B Benefits 5 Reduced/simplified PCB area Reduced package size Comparable power for large throughput Scalable to higher frequencies Simplified interface timing Standard interface DAC LVDS 32 lanes 4 layers JESD204 8 lanes 1 layer JESD204B Benefits 6 DAC DAC 10x10mm
JESD204 Timing Signals/Terminology TI Information – NDA Required Frame Clock • Data frame of the transport layer is aligned to the frame clock • Frame clock …
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