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Kami: A Framework for (RISC -V) HW Verification

Kami: A Framework for (RISC-V) HW VerificationMuraliVijayaraghavanJoonwonC hoi, Adam Chlipala,(Ben Sherman),Andy Wright, SizhuoZhang, Thomas Bourgeat, Arvind1 The RiscyExpedition by MITR iscyLibrary of Modules RiscyDesignsCircuits (FPGAs, ASICs)Formal Full-SystemVerification2 Chips with ProofsModular Verification of a Full-SystemIn-order CoreCoherent Cache Hierarchy(MSI protocol)In-order CoreCoherent Cache Hierarchy(MOSI protocol)..In-order CoreOOO CoreOOO CoreOOO Core(A optimizes A) Must be able to verify that optimization is correct independent of contextsMust be able to verify in presence of parameters instead of just in concrete settings3(A+B) (A +B) Semantics for Modular VerificationModuleStateTransitionTransit ionInputsOutputsA optimizes B IO sequences of A IO sequences of B4 Kami Verification Framework DSL in the Coq Proof Assistant for verif

Kami Verification Framework • DSL in the Coq Proof Assistant for verifying Bluespec-style H/W – Embodies the modular verification semantics

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