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The RISC-V Instruction Set Manual

The RISC-V Instruction Set ManualVolume I: Unprivileged ISAD ocument Version 20191213 Editors: Andrew Waterman1, Krste Asanovi c1,21 SiFive Inc.,2CS Division, EECS Department, University of California, 13, 2019 Contributors to all versions of the spec in alphabetical order (please contact editors to suggestcorrections): Arvind, Krste Asanovi c, Rimas Avi zienis, Jacob Bachmeyer, Christopher F. Bat-ten, Allen J. Baum, Alex Bradbury, Scott Beamer, Preston Briggs, Christopher Celio, ChuanhuaChang, David Chisnall, Paul Clayton, Palmer Dabbelt, Ken Dockser, Roger Espasa, Shaked Flur,Stefan Freudenberger, Marc Gauthier, Andy Glew, Jan Gray, Michael Hamburg, John Hauser,David Horner, Bruce Hoult, Bill Huffman, Alexandre Joannou, Olof Johansson, Ben Keller, DavidKruckemyer, Yunsup Lee, Paul Loewenstein, Daniel Lustig, Yatin Manerkar, Luc Maranget, Mar-garet Martonosi, Joseph Myers, Vijayanand Nagarajan, Rishiyur Nikhil, Jonas Oberhauser, StefanO Rear, Albert Ou, John Ousterhout, David Patterson, Christopher Pulte, Jose Renau, Josh Scheid,Colin Schmidt, Peter Sewell, Susmit Sarkar, Michael Taylor, Wesley Terpstra, Matt Thomas,Tommy Thorn, Caroline Trippel, Ray VanDeWalker, Muralidaran Vijayaraghavan, Megan Wachs,Andrew Waterman, Robert

Dec 13, 2019 · The RISC-V Instruction Set Manual Volume I: Unprivileged ISA Document Version 20191213 Editors: Andrew Waterman 1, Krste Asanovi´c,2 1SiFive Inc., 2CS Division, EECS Department, University of California, Berkeley andrew@sifive.com, krste@berkeley.edu

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This document is a derivative of \The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.1" released under the following license: c 2010{2017 Andrew Waterman, Yunsup Lee, ... Modi ed implicit hinting suggestion on JALR to support more e cient macro-op fusion of LUI/JALR and AUIPC/JALR pairs. i.

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The RISC-V Instruction Set Manual Volume I: Unprivileged ISA Document Version 20190608-Base-Ratified Editors: Andrew Waterman 1, Krste Asanovi´c,2 1SiFive Inc., 2CS Division, EECS Department, University of California, Berkeley andrew@sifive.com, krste@berkeley.edu

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Simpli ed the handling of existing hard-ware counters, removing privileged versions of the counters and the corresponding delta reg- ... RISC-V Privileged Architectures V1.10 7 Platform-Level Interrupt Controller (PLIC) 69 ... Chapter 1 Introduction This is a draft of the privileged architecture description document for RISC-V. Feedback welcome.

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Jul 12, 2016 · 30 1.9draft: Volume II: RISC-V Privileged Architectures XLEN-1 12 11 10 9 8 7 6 5 4 3 2 1 0 WPRI MEIE HEIE SEIE UEIE MTIE HTIE STIE UTIE MSIE HSIE SSIE USIE XLEN-12 1 1 1 1 1 1 1 1 1 1 1 1 Figure 3.11: Machine interrupt-enable register (mie). HTIP bits may be written by M-mode software to deliver timer interrupts to lower privilege levels.

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Register ABI Name Description Saver x0 zero Hard-wired zero — x1 ra Return address Caller x2 sp Stack pointer Callee x3 gp Global pointer — x4 tp Thread pointer — x5–7 t0–2 Temporaries Caller x8 s0/fp Saved register/frame pointer Callee x9 s1 Saved register Callee x10–11 a0–1 Function arguments/return values Caller

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The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2 Editors: Andrew Waterman 1, Krste Asanovi c;2 1SiFive Inc., 2CS Division, EECS Department, University of California, Berkeley andrew@sifive.com, krste@berkeley.edu May 7, 2017

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Figure 2 illustrates the RISC-V instruction length encoding convention. All the 32-bit instructions in the base ISA have their lowest two bits set to 11. The compressed 16-bit instruction-set extensions have their lowest two bits equal to 00, 01, or 10. Instruction-set extensions encoded with more than 32 bits have additional low-order bits set ...

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