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Lecture 04 RISC-V ISA - GitHub Pages

Lecture 04 RISC-V ISACSCE 513 Computer ArchitectureDepartment of Computer Science and Slides adapted from Computer Science 152: Computer Architecture and Engineering, Spring 2016 by Dr. George Michelogiannakisfrom UCB Reference contents CAQA COD textbook, chapter 22 Review: ISA Principles --Iron-code Summary Section Use general-purpose registers with a load-store architecture. Section Support these addressing modes: displacement (with an address offset size of 12 to 16 bits), immediate (size 8 to 16 bits), and register indirect. Section Support these data sizes and types: 8-, 16-, 32-, and 64-bit integers and 64-bit IEEE 754 floating-point numbers. Now we see 16-bit FP for deep learning in GPU Section Support these simple instructions , since they will dominate the number of instructions executed: load, store, add, subtract, move register-register, and shift. Section Compare equal, compare not equal, compare less, branch (with a PC-relative address at least 8 bits long), jump, call, and return.

What is RISC-V • RISC-V (pronounced "risk-five”) is a ISA standard – An open source implementation of a reduced instruction set computing (RISC) based instruction set architecture (ISA) – There was RISC-I, II, III, IV before • Most ISAs: X86, ARM, Power, MIPS, SPARC – Commercially protected by patents

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