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Category NameFmtRV32I BaseCategory NameRV mnemonicLoads Load ByteILB rd,rs1,immCSR Access Atomic R/WCSRRW rd,csr,rs1 Load HalfwordILH rd,rs1,immAtomic Read & Set BitCSRRS rd,csr,rs1 Load WordILW rd,rs1,immAtomic Read & Clear BitCSRRC rd,csr,rs1 Load Byte UnsignedILBU rd,rs1,imm Atomic R/W ImmCSRRWI rd,csr,imm Load Half UnsignedILHU rd,rs1,immAtomic Read & Set Bit ImmCSRRSI rd,csr,imm Stores Store ByteSSB rs1,rs2,immAtomic Read & Clear Bit ImmCSRRCI rd,csr,imm Store HalfwordSSH rs1,rs2,immChange Level Env. CallECALL Store WordSSW rs1,rs2,immEnvironment Breakpoint EBREAK Shifts Shift Left RSLL rd,rs1,rs2 Environment ReturnERET Shift Left ImmediateISLLI rd,rs1,shamt Trap Redirect to SupervisorMRTS Shift RightRSRL rd,rs1,rs2 Redirect Trap to HypervisorMRTH Shift Right ImmediateISRLI rd,rs1,shamt Hypervisor Trap to SupervisorHRTS Shift Right ArithmeticRSRA rd,rs1,rs2 Interrupt Wait for Interrupt WFI Shift Right Arith ImmISRAI rd,rs1,shamt MMU Supervisor rs1 Arithmetic ADDRADD rd,rs1,rs2 ADD ImmediateIADDI rd,rs1,imm SUBtractRSUB rd,rs1,rs2 Load Upper ImmULUI rd,imm Add Upper I

RISC-V Integer Base (RV32I/64I/128I), privileged, and optional compressed extension (RVC). Registers x1-x31 and the pc are 32 bits wide in RV32I, 64 in RV64I, and 128 in RV128I (x0=0). RV64I/128I add 10 instructions for the wider formats. The RVI base of <50 classic integer RISC instructions is required.

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  Icsr, Risc v

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