Free & Open Reference Card

1 Category NameFmtRV32I BaseCategory NameRV mnemonicLoads Load ByteILB rd,rs1,immCSR Access Atomic R/WCSRRW rd,csr,rs1 Load HalfwordILH rd,rs1,immAtomic Read & Set BitCSRRS rd,csr,rs1 Load WordILW rd,rs1,immAtomic Read & Clear BitCSRRC rd,csr,rs1 Load Byte UnsignedILBU rd,rs1,imm Atomic R/W ImmCSRRWI rd,csr,imm Load Half UnsignedILHU rd,rs1,immAtomic Read & Set Bit ImmCSRRSI rd,csr,imm Stores Store ByteSSB rs1,rs2,immAtomic Read & Clear Bit ImmCSRRCI rd,csr,imm Store HalfwordSSH rs1,rs2,immChange Level Env. CallECALL Store WordSSW rs1,rs2,immEnvironment Breakpoint EBREAK Shifts Shift Left RSLL rd,rs1,rs2 Environment ReturnERET Shift Left ImmediateISLLI rd,rs1,shamt Trap Redirect to SupervisorMRTS Shift RightRSRL rd,rs1,rs2 Redirect Trap to HypervisorMRTH Shift Right ImmediateISRLI rd,rs1,shamt Hypervisor Trap to SupervisorHRTS Shift Right ArithmeticRSRA rd,rs1,rs2 Interrupt Wait for Interrupt WFI Shift Right Arith ImmISRAI rd,rs1,shamt MMU Supervisor rs1 Arithmetic ADDRADD rd,rs1,rs2 ADD ImmediateIADDI rd,rs1,imm SUBtractRSUB rd,rs1,rs2 Load Upper ImmULUI rd,imm Add Upper Imm to PCUAUIPC rd,immCategory NameFmtRVCRVI equivalentLogical XORRXOR rd,rs1,rs2 Loads Load rd ,rs1 ,immLW rd ,rs1 ,imm*4 XOR ImmediateIXORI rd,rs1.

2 ImmLoad Word rd,immLW rd,sp,imm*4OR ROR rd,rs1,rs2 Load rd ,rs1 ,immLD rd ,rs1 ,imm*8OR ImmediateIORI rd,rs1,immLoad Double rd,immLD rd,sp,imm*8 ANDRAND rd,rs1,rs2 Load rd ,rs1 ,immLQ rd ,rs1 ,imm*16 AND ImmediateIANDI rd,rs1,immLoad Quad rd,immLQ rd,sp,imm*16 Compare Set <RSLT rd,rs1,rs2 Stores Store rs1 ,rs2 ,immSW rs1 ,rs2 ,imm*4 Set < ImmediateISLTI rd,rs1,immStore Word rs2,immSW rs2,sp,imm*4 Set < UnsignedRSLTU rd,rs1,rs2 Store rs1 ,rs2 ,immSD rs1 ,rs2 ,imm*8 Set < Imm UnsignedISLTIU rd,rs1,immStore Double rs2,immSD rs2,sp,imm*8 Branches Branch =SBBEQ rs1,rs2,immStore rs1 ,rs2 ,immSQ rs1 ,rs2 ,imm*16 Branch SBBNE rs1,rs2,immStore Quad rs2,immSQ rs2,sp,imm*16 Branch <SBBLT rs1,rs2,immArithmetic rd,rs1 ADD rd,rd,rs1 Branch SBBGE rs1,rs2,immADD rd,rs1 ADDW rd,rd,imm Branch < UnsignedSBBLTU rs1,rs2,imm ADD rd,immADDI rd,rd,imm Branch UnsignedSBBGEU rs1,rs2,imm ADD Word rd,immADDIW rd,rd,immJump & Link J&LUJJAL rd,imm ADD SP Imm * x0,immADDI sp,sp,imm*16 Jump & Link RegisterUJJALR rd,rs1,imm ADD SP Imm * rd',immADDI rd',sp,imm*4 Synch Synch threadIFENCE Load rd,immADDI rd,x0,imm Synch Instr & Load Upper rd,imm LUI rd,immSystem System rd,rs1 ADD rd,rs1,x0 System BREAKISBREAK rd,rs1 SUB rd,rd,rs1 Counters ReaD CYCLEIRDCYCLE rd Shifts Shift Left rd,immSLLI rd,rd,imm ReaD CYCLE upper HalfIRDCYCLEH rd Branches Branch= rs1 ,immBEQ rs1',x0,imm ReaD TIMEIRDTIME rd Branch rs1.

3 ImmBNE rs1',x0,imm ReaD TIME upper HalfIRDTIMEH rd Jump imm JAL x0,imm ReaD INSTR RETiredIRDINSTRET rd Jump rd,rs1 JALR x0,rs1,0 ReaD INSTR upper HalfIRDINSTRETH rd Jump & Link J& imm JAL ra,imm Jump & Link rs1 JALR ra,rs1,0 System Env. CRRCIICSSSCIWSBCLUCSUJCBCJRISC-V Integer Base (RV32I/64I/128I), privileged, and optional compressed extension (RVC). Registers x1-x31 and the pc are 32 bits wide in RV32I, 64 in RV64I, and 128 in RV128I (x0=0). RV64I/128I add 10 instructions for the wider formats. The RVI base of <50 classic integer RISC instructions is required. Every 16-bit RVC instruction matches an existing 32-bit RVI instruction. See Instruction Formats16-bit (RVC) Instruction FormatsSRAI{W|D} rd,rs1,shamtADD{W|D} rd,rs1,rs2 ADDI{W|D} rd,rs1,immSUB{W|D} rd,rs1,rs2 Optional Compressed (16-bit) Instruction Extension: RVC SRL{W|D} rd,rs1,rs2 SRLI{W|D} rd,rs1,shamtSRA{W|D} rd,rs1,rs2S{D|Q} rs1,rs2,immSLL{W|D} rd,rs1,rs2 SLLI{W|D} rd,rs1,shamtL{D|Q} rd,rs1,immL{W|D}U rd,rs1,imm Free & Open Reference Card +RV{64,128}Base Integer Instructions.

4 RV32I, RV64I, and RV128 IRV Privileged InstructionsCategory NameFmtRV32M (Multiply-Divide)Multiply MULtiplyRMUL rd,rs1,rs2 MULtiply upper HalfRMULH rd,rs1,rs2 MULtiply Half Sign/UnsRMULHSU rd,rs1,rs2 MULtiply upper Half UnsRMULHU rd,rs1,rs2 Divide DIVideRDIV rd,rs1,rs2 DIVide UnsignedRDIVU rd,rs1,rs2 Remainder REMainderRREM rd,rs1,rs2 REMainder UnsignedRREMU rd,rs1,rs2 Category NameFmtRV32A (Atomic)Load Load rd,rs1 Store Store rd,rs1,rs2 Swap rd,rs1,rs2 Add rd,rs1,rs2 Logical rd,rs1,rs2 rd,rs1, rd,rs1,rs2 Min/Max rd,rs1, rd,rs1,rs2 MINimum rd,rs1,rs2 MAXimum rd,rs1,rs2 Category NameFmtRV32{F|D|Q} (HP/SP,DP,QP Fl Pt)Move Move from IntegerRFMV.

5 {H|S}.X rd,rs1 FMV.{D|Q}.X rd,rs1 Move to {H|S} rd, {D|Q} rd,rs1 Convert Convert from IntRFCVT.{H|S|D|Q}.W rd,rs1 FCVT.{H|S|D|Q}.{L|T} rd,rs1 Convert from Int UnsignedRFCVT.{H|S|D|Q}.WU rd,rs1 FCVT.{H|S|D|Q}.{L|T}U rd,rs1 Convert to {H|S|D|Q} rd,rs1 FCVT.{L|T}.{H|S|D|Q} rd,rs1 Convert to Int {H|S|D|Q} rd,rs1 FCVT.{L|T}U.{H|S|D|Q} rd,rs1 Load LoadIFL{W,D,Q} rd,rs1,immStore StoreSFS{W,D,Q} rs1,rs2,immRegisterABI NameSaverDescriptionArithmetic ADDRFADD.{S|D|Q} rd,rs1,rs2x0zero ---Hard-wired zeroSUBtractRFSUB.{S|D|Q} rd,rs1,rs2x1ra CallerReturn addressMULtiplyRFMUL.{S|D|Q} rd,rs1,rs2x2sp CalleeStack pointerDIVideRFDIV.{S|D|Q} rd,rs1,rs2x3gp ---Global pointer SQuare RooTRFSQRT.

6 {S|D|Q} rd,rs1x4tp ---Thread pointerMul-Add Multiply-ADDRFMADD.{S|D|Q} rd,rs1,rs2,rs3x5-7t0-2 CallerTemporariesMultiply-SUBtractRFMSUB .{S|D|Q} rd,rs1,rs2,rs3x8s0/fp CalleeSaved register/frame pointer Negative Multiply-SUBtractRFNMSUB.{S|D|Q} rd,rs1,rs2,rs3x9s1 CalleeSaved registerNegative Multiply-ADDRFNMADD.{S|D|Q} rd,rs1,rs2,rs3x10-11a0-1 CallerFunction arguments/return valuesSign Inject SiGN sourceRFSGNJ.{S|D|Q} rd,rs1,rs2x12-17a2-7 CallerFunction arguments Negative SiGN sourceRFSGNJN.{S|D|Q} rd,rs1,rs2x18-27s2-11 CalleeSaved registersXor SiGN sourceRFSGNJX.{S|D|Q} rd,rs1,rs2x28-31t3-t6 CallerTemporariesMin/Max MINimumRFMIN.{S|D|Q} rd,rs1,rs2f0-7 ft0-7 CallerFP temporaries MAXimumRFMAX.{S|D|Q} rd,rs1,rs2f8-9 fs0-1 CalleeFP saved registers Compare Compare Float =RFEQ.

7 {S|D|Q} rd,rs1,rs2f10-11 fa0-1 CallerFP arguments/return values Compare Float <RFLT.{S|D|Q} rd,rs1,rs2f12-17 fa2-7 CallerFP arguments Compare Float RFLE.{S|D|Q} rd,rs1,rs2f18-27 fs2-11 CalleeFP saved registers Categorization Classify TypeRFCLASS.{S|D|Q} rd,rs1f28-31 ft8-11 Caller FP temporaries Configuration Read StatusRFRCSR rdRead Rounding ModeRFRRM rdRead FlagsRFRFLAGS rdSwap Status RegRFSCSR rd,rs1 Swap Rounding ModeRFSRM rd,rs1 Swap FlagsRFSFLAGS rd,rs1 Swap Rounding Mode ImmIFSRMI rd,immSwap Flags ImmIFSFLAGSI rd,immRISC-V calling convention and five optional extensions: 10 multiply-divide instructions (RV32M); 11 optional atomic instructions (RV32A); and 25 floating-point instructions each for single-, double-, and quadruple-precision (RV32F, RV32D, RV32Q).

8 The latter add registers f0-f31, whose width matches the widest precision, and a floating-point control and status register fcsr. Each larger address adds some instructions: 4 for RVM, 11 for RVA, and 6 each for RVF/D/Q. Using regex notation, {} means set, so L{D|Q} is both LD and LQ. See (8/21/15 revision)AMOMINU.{D|Q} rd,rs1,rs2 AMOMAXU.{D|Q} rd,rs1,rs2 Three Optional Floating-Point Instruction Extensions: RVF, RVD, & RVQ +RV{64,128}RISC-V Calling ConventionAMOMAX.{D|Q} rd,rs1,rs2 AMOADD.{D|Q} rd,rs1,rs2 AMOXOR.{D|Q} rd,rs1,rs2 AMOAND.{D|Q} rd,rs1,rs2 AMOOR.{D|Q} rd,rs1,rs2 AMOMIN.{D|Q} rd,rs1,rs2LR.{D|Q} rd,rs1SC.{D|Q} rd,rs1,rs2 AMOSWAP.{D|Q} rd,rs1,rs2 REMU{W|D} rd,rs1,rs2 Optional Atomic Instruction Extension: RVA +RV{64,128}REM{W|D} rd,rs1,rs2 MUL{W|D} rd,rs1,rs2 DIV{W|D} rd,rs1,rs2 Free & Open Reference Card ( ) +RV{64,128}Optional Multiply-Divide Instruction Extension: RVM