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Lecture 13: SRAM

introduction toCMOS VLSID esignLecture 13: SRAMD avid HarrisHarvey Mudd CollegeSpring 200413: SRAMS lide 2 cmos vlsi DesignOutlineqMemory ArraysqSRAM Architecture SRAM Cell Decoders Column Circuitry Multiple PortsqSerial Access Memories13: SRAMS lide 3 cmos vlsi DesignMemory ArraysMemory ArraysRandom Access MemorySerial Access MemoryContent Addressable Memory(CAM)Read/Write Memory(RAM)(Volatile)Read Only Memory(ROM)(Nonvolatile)Static RAM(SRAM)Dynamic RAM(DRAM)Shift RegistersQueuesFirst InFirst Out(FIFO)Last InFirst Out(LIFO)Serial InParallel Out(SIPO)Parallel InSerial Out(PISO)Mask ROMP rogrammableROM(PROM)ErasableProgrammable ROM(EPROM)ElectricallyErasableProgrammab leROM(EEPROM)Flash ROM13: SRAMS lide 4 cmos vlsi DesignArray Architectureq2nwordsof 2mbitseachqIf n >> m, fold by 2kinto fewer rowsof more columnsqGood regularity easy to designqVery high density if good cells are usedrow decodercolumndecodernn-kk2m bitscolumncircuitrybitline conditioningmemory cells:2n-k rows x2m+k columnsbitlineswordlines13: SRAMS lide 5 cmos vlsi Design12T SRAM CellqBasic building block: SRAM Cell Holds one bit of information, like a latch Must be read and writtenq12-transistor (12T) SRAM cell Use a simple latch connected to bitlinebitwritewrite_breadread_b13: SRAMS lide 6 cmos vlsi Design6T SRAM CellqCell size accounts for most of array size Reduce cell size at expense of co

Introduction to CMOS VLSI Design Lecture 13: SRAM David Harris Harvey Mudd College Spring 2004. 13: SRAM CMOS VLSI Design Slide 2 Outline qMemory Arrays qSRAM Architecture – SRAM Cell – Decoders – Column Circuitry – …

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