Transcription of Lecture 13: SRAM
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Lecture 13: SRAM
Introduction toCMOS VLSID esignLecture 13: SRAMD avid HarrisHarvey Mudd CollegeSpring 200413: SRAMS lide 2 CMOS VLSI DesignOutlineqMemory ArraysqSRAM Architecture SRAM Cell Decoders Column Circuitry Multiple PortsqSerial access Memories13: SRAMS lide 3 CMOS VLSI DesignMemory ArraysMemory ArraysRandom access MemorySerial access MemoryContent Addressable memory (CAM)Read/Write memory (RAM)(Volatile)Read Only memory (ROM)(Nonvolatile) static RAM(SRAM)Dynamic RAM(DRAM)Shift RegistersQueuesFirst InFirst Out(FIFO)Last InFirst Out(LIFO)Serial InParallel Out(SIPO)Parallel InSerial Out(PISO)Mask ROMP rogrammableROM(PROM)ErasableProgrammable ROM(EPROM)ElectricallyErasableProgrammab leROM(EEPROM)Flash ROM13: SRAMS lide 4 CMOS VLSI DesignArray Architectureq2nwordsof 2mbitseachqIf n >> m, fold by 2kinto fewer rowsof more columnsqGood regularity easy to designqVery high density if good cells are usedrow decodercolumndecodernn-kk2m bitscolumncircuitrybitline conditioningmemory cells:2n-k rows x2m+k columnsbitlineswordlines13: SRAMS lide 5 CMOS VLSI Design12T SRAM CellqBasic building block: SRAM Cell H
Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) ... Static CMOS Pseudo-nMOS word0 word1 word2 word3 A1 A0 A1 word A0 1 1 1/2 2 4 8 16 word A0 A1 1 1 1 1 4 word0 8 word1 word2 word3 ... qBut always dissipates static power bit bit_b sense_b sense N1 N2 N3 P1 P2. 13: SRAM CMOS …
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