Transcription of Memcon: TuningDDR4 for Power Performance
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Memcon: TuningDDR4 for Power Performance
Tuning ddr4 for Power and PerformanceMike MichelettiProduct Manager Teledyne LeCroyAgenda Introduction ddr4 Technology Expanded role of MRS Power Features Examined Reliability Features Examined Performance Features Examined8/22/20132 ddr4 Goals & Motivations Spec development started in 2005; Officical JEDEC release Aug 2012 Up to Gbps (per pin) 2x Bandwidth Single Ended Signaling Similar clockingEvolutionary Path 8 Bit prefetch, same core frequency Lower Cost 30-40% Power saving (vs DDR3L), tCAL, LP-ASR, Power Savings C/A parity, CRC, MPR readout, ReliabilityAnalysts: 50% market penetration by 2015/2016 PowerReliability (RAS)PerformanceSignallingTe s tNew ddr4 Features Categorized4 TCSRTCARCS to CMD Latency (TCAL) VDDQ TermMax Power Saving Page sizeDBI3 DSWrite CRCCA ParityMultipurpose Register (MPR) Readout2133 to 3200 MT/s signalingBank GroupsFine Granularity RefreshSelf Refresh AbortGear Down ModeInternal Vref DQDQ Training with MPRPer DRAM AddressabilityDDR4 Compared to DDR38/22/20135 Spec ItemsDDR3 ddr4 Density / Speed512 Mbp~8Gb ~ ~ ~ (VDD/VDDQ/VPP) ( ) Vref (VDD/2)Internal Vref(Req.)
Power Reliability (RAS) Performance Signalling Test New DDR4 Features Categorized 4 TCSR TCAR CS to CMD Latency (TCAL) VDDQ Term Max Power Saving Mode 0.5KB Page size
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