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MOS Transistors - Duke Electrical and Computer Engineering

1 1 MOS Transistors Silicon substrate doped with impurities Adding or cutting away insulating glass (SiO2) Adding wires made of polycrystalline silicon (polysilicon, poly) or metal, insulated from the substrate by SiO2 Drain Source Gate n n Drain Source Gate SiO2 (insulator) p-type (doped) substrate Drain Source Gate nMOS transistor pMOS transistor channel Width W Length L Conductor (poly) 2 MOS transistor Switches N a b s N-switch a b s S = 0 S = 1 Good 0, Poor 1 0 1 0 1 (degraded) 2 3 MOS transistor Switches P-switch a b s P a b s S = 1 S = 0 Good 1, Poor 0 1 0 1 0 (degraded) a b s s CMOS switch a b s C S = 0 S = 1 a Good 0 Good 1 (Transmission gate) b s s 4 Signal Strength Strength of signal How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0 But degraded or weak 1 pMOS pass strong 1 But degraded or weak 0 Thus nMOS are best for pull-down network 3 5 Pass Transistors Transistors can be used as switches 6 Transmission Gates Pass Transistors produce degraded outputs Transmission gates pass both 0 and 1 well 4 7 Complementary CMOS Complementary CMOS logic gates nMOS pull-down network pMOS pull-up network static CMOS Pull-up OFF Pull-up ON Pull-down OFF Z (float) 1 Pull-down ON 0 X (not allowed) 8 Series and Parallel nMOS

– Pull-up circuit corresponds to pull-up graph 11 21 Graph Models a b c Gnd d a b d c Pull-down circuit Gnd ... Gate-Level Mux Design • How many transistors are needed? 20 14 27 ... e.g. VHDL, Verilog • Example: Consider the carry function c o = ab + bc + c i a 22 43

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