MOS Transistors - Duke Electrical and Computer Engineering

1 1 1 MOS Transistors Silicon substrate doped with impurities Adding or cutting away insulating glass (SiO2) Adding wires made of polycrystalline silicon (polysilicon, poly) or metal, insulated from the substrate by SiO2 Drain Source Gate n n Drain Source Gate SiO2 (insulator) p-type (doped) substrate Drain Source Gate nMOS transistor pMOS transistor channel Width W Length L Conductor (poly) 2 MOS transistor Switches N a b s N-switch a b s S = 0 S = 1 Good 0, Poor 1 0 1 0 1 (degraded) 2 3 MOS transistor Switches P-switch a b s P a b s S = 1 S = 0 Good 1, Poor 0 1 0 1 0 (degraded) a b s s CMOS switch a b s C S = 0 S = 1 a Good 0 Good 1 (Transmission gate) b s s 4 Signal Strength Strength of signal How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0 But degraded or weak 1 pMOS pass strong 1 But degraded or weak 0 Thus nMOS are best for pull-down network 3 5 Pass Transistors Transistors can be used as switches 6 Transmission Gates Pass Transistors produce degraded outputs Transmission gates pass both 0 and 1 well 4 7 Complementary CMOS Complementary CMOS logic gates nMOS pull-down network pMOS pull-up network static CMOS Pull-up OFF Pull-up ON Pull-down OFF Z (float) 1 Pull-down ON 0 X (not allowed) 8 Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON 5 Conduction Complement Complementary CMOS gates always produce 0 or 1 Ex: NAND gate Series nMOS.

2 Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pMOS Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel 10 CMOS Logic Gates-1 Inverter Input Output a a VDD Gnd Pull-down Pull-up path path 2-input NAND Gnd VDD a b a b Pull-down Pull-up tree tree a b z z 0 0 Z 0 1 Z 1 0 Z 1 1 0 a b z 0 0 1 0 1 1 1 0 1 1 1 Z Pull-down Pull-up truth table truth table a b z 0 0 1 0 1 1 1 0 1 1 1 0 NAND truth table 6 11 CMOS Logic Gates-2 2-input NOR Gnd VDD a b a b Pull-down Pull-up tree tree a b z z 0 0 Z 0 1 0 1 0 0 1 1 0 a b z 0 0 1 0 1 Z 1 0 Z 1 1 Z Pull-down Pull-up truth table truth table a b z 0 0 1 0 1 0 1 0 0 1 1 0 NOR truth table Generalize to n-input NAND and n-input NOR? There is always (for all input combinations) a path from either 1 or 0 to the output No direct path from 1 to 0 (low power dissipation) Fully restored logic No ratio-ing is necessary (ratio-less logic) 12 CMOS Compound (Complex) Gates-1 What function is implemented by this circuit ?

3 Z c d Gnd a b VDD a b c d 7 13 Compound Gates-2 VDD a b a How to implement F = ab + bc + ca? F = ab + bc + ca b a c c b a b VDD Gnd F F Gnd c c 14 Compound Gates Compound gates can do any inverting function Ex: 8 15 Example: O3AI 16 CMOS Multiplexers a b s ss s F = as + bs Transmission gate implementation ( 4 Transistors ) Complex gate implementation based on F = as + bs requires 10 Transistors Assume s is available 9 17 And-Or-Invert (AOI) Gates a b c d e f g h F Pull-up network a b c F Gnd h f g d e 18 Or-And-Invert (OAI) Gate a b c d e f g h F a b c Pull-up network d e f g h Gnd F Generally, complex CMOS gates can be derived directly from maxterms of the function (as in a Karnaugh map) 10 19 Designing Complex Gates Using K-Maps a b c Pull-up network d 00 01 11 10 00 01 11 10 ab cd 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 F = ab + bd + bc = b(a+d+c) F = b + acd (how many Transistors ?)

4 F 20 Graph Models How to generate pull-up circuit from the pull-down circuit ? Draw pull-down graph for pull-down circuit Every vertex is a source-drain connection Every edge is an nMOS transistor Generate pull-up graph from the pull-down graph Add vertex for every region of pull-down graph Add edge between between vertices lying in adjacent regions Pull-up circuit corresponds to pull-up graph 11 21 Graph Models a b c Gnd d a b d c Pull-down circuit Gnd VDD Pull-up circuit I1 I2 I3 I3 I1 I2 a b d c VDD Pull-up Pull-down 22 Tristates Tristate buffer produces Z when not enabled EN A Y 0 0 Z 0 1 Z 1 0 0 1 1 1 12 23 Nonrestoring Tristate Transmission gate acts as tristate buffer Only two Transistors But nonrestoring Noise on A is passed on to Y 24 Tristate Inverter Tristate

5 Inverter produces restored output Violates conduction complement rule Because we want a Z output 13 25 Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y 0 X 0 0 0 X 1 1 1 0 X 0 1 1 X 1 26 Gate-Level Mux design How many Transistors are needed? 20 14 27 Transmission Gate Mux Nonrestoring mux uses two transmission gates Only 4 Transistors 28 Inverting Mux Inverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thing Noninverting multiplexer adds an inverter 15 29 CMOS Exclusive-Nor Gate a b F = a b 8- transistor implementation TG1 TG2 a b TG1 TG2 F 0 0 nonconducting conducting B (1) 0 1 nonconducting conducting B (0) 1 0 conducting nonconducting B (0) 1 1 conducting nonconducting B (1) Better, 6- transistor implementation is possible!

6 30 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates 16 31 D Latch When CLK = 1, latch is transparent D flows through to Q like a buffer When CLK = 0, the latch is opaque Q holds its old value independent of D transparent latch or level-sensitive latch 32 Memory Elements: Latches and Flip-Flops Difference between a latch and a flip-flop? C C Clock Q Q D Positive level-sensitive D-latch Recirculating latch How to design negative level-sensitive D-latch? 17 33 D Latch design Multiplexer chooses D or old Q 34 Memory Elements: Latches and Flip-Flops Clock = 0 Q Q Q Q D Clock = 1 Q changes faster than Q 18 35 D Latch Operation 36 D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value positive edge-triggered flip-flop, master-slave flip-flop 19 37 D Flip-flop design Built from master and slave D latches 38 Flip-Flop design D QM Q Clock = 0 Q QM Clock = 1 How do we obtain the Q output?

7 Q Clock C C C C Positive edge-triggered D flip-flop QM D Master Slave 20 39 D Flip-flop Operation 40 Race Condition Back-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition 21 41 Nonoverlapping Clocks Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew We will use them in this class for safe design Industry manages skew more carefully instead 42 design Representation Levels design domains Behavioral Structural Physical Gajski and Kuhn s Y-chart (layered like an onion) Behavioral Structural Physical (geometric) Chip Cells Polygons Transistors Gates Processor Boolean equations Differential equations Algorithms Hardware description languages commonly used at behavioral level, vhdl , Verilog Example: Consider the carry function co = ab + bc + cia 22 43 Verilog Example (Behavioral) module carry (co, a, b, ci); output co; input a, b, ci; assign co = (a & b) | (a & ci) | (b end module Boolean equation form: Boolean truth table form: primitive carry (co, a, b, ci); output co; input a, b, ci; table // a b c co 1 1 ?)

8 : 1; 1 ? 1 : 1; ? 1 1 : 1; 0 0 ? : 0; 0 ? 0 : 0; ? 0 0 : 0; end table end module Timing information: module carry (co, a, b, ci); output co; input a, b, ci; Wire #10 co = (a & b) | (a & ci) | (b end module co changes 10 time units after a, b, or c changes 44 Verilog Example (Structural) module add4 (s, c4, ci, a, b); output [3:0] s; output [3:0] c4; input [3:0] a, b; input ci; wire [2:0] co; add a0 (co[0], s[0], a[0], b[0], ci); add a1 (co[1], .., b[1], co[0]); add a2 (co[2], .., , co[1]); add a3 (c4, s[3], a[3], b[3], co[2]); end module Structural representation of 4-bit adder (top-down) : module add (co, s, a, b, ci); output s, co; input a, b, ci; sum s1 (s, a, b, ci); carry c1 (co, a, b, ci); end module internal 3-bit signal module carry (co, a, b, ci); output co; input a, b, ci; wire x, y, z; and g1 (y, z, b); and g2 (z, b, ci); and g3 (z, a, ci); or g4 (co, x, y, z); end module Technology-independent)