Transcription of MPC5748G, MPC5748G Microcontroller Data Sheet
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MPC5748G, MPC5748G Microcontroller Data Sheet
MPC5748 GMPC5748G MicrocontrollerData SheetFeatures 2 x 160 MHz Power Architecture e200Z4 Dual issue,32-bit CPU Single precision floating point operations 8 KB instruction cache and 4 KB data cache Variable length encoding (VLE) for significant codedensity improvements 1 x 80 MHz Power Architecture e200Z2 Single issue,32-bit CPU Using variable length encoding (VLE) forsignificant code size footprint reduction End to end ECC All bus masters, for example, cores generate singleerror correction, double error detection (SECDED)code for every bus transaction SECDED covers 64-bit data and 29-bit address Memory interfaces 6 MB on-chip flash supported with the flashcontroller 3 x flash page buffers (3 port flash controller) 768 KB on-chip SRAM across three RAM ports Clock interfaces 8-40 MHz external crystal (F)
3 x FCD 3 x eMIOS + BCTU 3-core INTC DMA and 2 x chmux 1 x CRC 3 x SA-PF buffers 6 MB array (inc EEE) E2 E-ECC Triple ported 64-bit wide RAM 256 KB array 3xRAM E2 E-ECC 256 KB array 256 KB array LPU_CTL 3 x DSMC 2 x DSMC *All FlexCANs optionally support CAN FD Figure 1. MPC5748G block diagram 2 Family comparison
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