MPC5748G, MPC5748G Microcontroller Data Sheet

1 MPC5748 GMPC5748G MicrocontrollerData SheetFeatures 2 x 160 MHz Power Architecture e200Z4 Dual issue,32-bit CPU Single precision floating point operations 8 KB instruction cache and 4 KB data cache Variable length encoding (VLE) for significant codedensity improvements 1 x 80 MHz Power Architecture e200Z2 Single issue,32-bit CPU Using variable length encoding (VLE) forsignificant code size footprint reduction End to end ECC All bus masters, for example, cores generate singleerror correction, double error detection (SECDED)code for every bus transaction SECDED covers 64-bit data and 29-bit address Memory interfaces 6 MB on-chip flash supported with the flashcontroller 3 x flash page buffers (3 port flash controller) 768 KB on-chip SRAM across three RAM ports Clock interfaces 8-40 MHz external crystal (FXOSC) 16 MHz IRC (FIRC) 128 KHz IRC (SIRC) 32 KHz external crystal (SXOSC) Clock Monitor Unit (CMU) Frequency modulated phase-locked loop (FMPLL) Real Time Counter (RTC) 2x System Memory Protection Unit (SMPU)

2 Each with16 region descriptors and 16-byte region granularity 16 Semaphores to manage access to shared resource Interrupt controller (INTC) capable of routinginterrupts to any CPU Multiple crossbar switch architecture for concurrentaccess to peripherals, flash, and RAM from multiplebus masters 32-channels eDMA controller with multiple transferrequest sources using DMAMUX Boot Assist Flash (BAF) supports internal flashprogramming via a serial link (LIN / SCI) Analog Two analog-to-digital converters (ADC), one 10-bitand one 12-bit Three analogue comparators Cross Trigger Unit to enable synchronization ofADC conversions with a timer event from theeMIOS or from the PIT Communication Four Deserial Peripheral Interface (DSPI) Six Serial Peripheral interface (SPI) 18 serial communication interface (LIN) modules Eight enhanced FlexCAN3 with FD support Four inter-IC communication interface (IIC) One USB OTG Controller (USB_0) and One USBSPH Controller (USB_1) with ULPI Interface.

3 ENET complex (10/100 Ethernet) that supportsMulti queue with AVB support, 1588, and MII/RMII 2 x ENET with L2 switch Secure Digital Hardware Controller (uSDHC) Dual-channel FlexRay Controller Audio 3 x Synchronous Audio Interface (SAI) Fractional clock dividers (FCD) operating inconjunction with the SAIs Configurable I/O domains supporting FLEXCAN,LINFlex, Ethernet, USB, MLB, uSDHC and generalI/O Supports wake-up from low power modes via theWKPU controller On-chip voltage regulator (VREG) Debug functionality e200Z2 core:NDI per IEEE-ISTO 5001-2008 Class3+ e200Z4 core(s): NDI per IEEE-ISTO 5001-2008 Class 3+NXP SemiconductorsDocument Number MPC5748 GData Sheet : Technical DataRev.

4 6, 11/2018 NXP reserves the right to change the production detail specifications as may berequired to permit improvements in the design of its products. Timer 16 Periodic Interrupt Timers (PITs) Three System Timer Module (STM) Four Software WatchDog Timers (SWT) 96 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE ) (cJTAG) Security Hardware Security Module (HSMv2) Password and Device Security (PASS and TDM) supporting advanced censorship and life-cycle management One Fault Collection and Control Unit (FCCU)

5 To collect faults and issue interrupts Functional Safety ISO26262 ASIL compliance Multiple operating modes Includes enhanced low power operationMPC5748G Microcontroller Data Sheet , Rev. 6, 11/20182 NXP SemiconductorsTable of Contents1 Block valid orderable parts .. Information .. maximum operating regulator electrical monitor electrical current discharge (ESD) Compatibility (EMC) specifications @ V electrical specifications @ specifications @ 5 V electrical specifications @ 5 V pad electrical electrical operating requirements and electrical Comparator (CMP) electrical and PLL interfaces oscillator electrical kHz Oscillator electrical specifications.

6 MHz RC Oscillator electrical KHz Internal RC oscillator Electricalspecifications .. electrical specifications .. memory program and erase memory Array Integrity and Margin memory module life retention vs program/erase memory AC timing read wait state and address pipeline controlsettings .. electrical switching (MLB) electrical 3-pin interface DC 3-pin interface electrical electrical timing electrical specifications .. interface timing .. interrupt timing (IRQ pin)..657 Thermal package dimensions .. pinouts and signal sequence execution sequence Microcontroller Data Sheet , Rev.

7 6, 11/2018 NXP Semiconductors31 Block diagram4 KB d-cache8 KB i-cacheNexus 3+SPFP-APU64-bit AHBE2 E-ECC160 MHz e200z4 Peripheral bridgeE2 E-ECCF lash160 MHz e200z4 Low powerunit interfaceE2 E-ECC64-bit dataSMPU64-bit AHBE2 E-ECCN exus 3+80 MHz e200z2 FlexrayMLB150 HSMuSDHCE thernet(ENET)Ethernet SwitcheDMAHS_USBSPHS ystem bus mastersSystemHS_USBOTG128 KHzSIRC2 x MEMUWKPUBAFFMPLLRTC/API4 x SWTs16 x SEMA416 x PIT-RTI32 KHzSXOSC8 40 MHzFXOSCP adkeepersupportRegisterprotectionMC_CGM, MC_PCU,MC_ME,MC_RGMSTCU(MBIST/LBIST)SIUL 3 x STMPMC16 MHz FIRCDEBUG/JTAGFCCUPASSSSCMCMUTDMP eripheral clusters80 ch 10-bit ADC0(mix int and ext)64 ch 12-bit ADC1(mix int and ext)1 x FlexCAN(PN)7 x FlexCAN1x 18 LinFlex4 x I2C3 x analogcomparator (CMP)4 x DSPI6 x SPI3 x SAI3 x FCD3 x eMIOS + BCTU3-core INTCDMA and 2 x chmux1 x CRC3 x SA-PF buffers6 MB array (inc EEE)E2 E-ECCT riple ported64-bit wide RAM256 KB array3xRAME2 E-ECC256 KB array256 KB arrayLPU_CTL2 x DSMC3 x DSMC*All FlexCANs optionally support CAN FDFigure 1.

8 MPC5748G block diagram2 Family comparisonThe following table provides a summary of the different members of the MPC5748 Gfamily and their proposed features. This information is intended to provide anunderstanding of the range of functionality offered by this family. For full details of all ofthe family derivatives please contact your marketing diagramMPC5748G Microcontroller Data Sheet , Rev. 6, 11/20184 NXP SemiconductorsNOTEAll optional features (Flash memory, RAM, Peripherals) startwith lowest peripheral number (for example: STM_0) ormemory address and end at the highest available peripheralnumber or memory address (for example: MPC574xC have 2 STM, ending with STM_1).

9 Table 1. MPC5748G Family Comparison1 FeatureMPC5747 CMPC5748 CMPC5746 GMPC5747 GMPC5748 GCPUse200z4e200z2e200z4e200z2e200z4e200z 4e200z2e200z4e200z4e200z2e200z4e200z4e20 0z2 FPUe200z4e200z4e200z4e200z4e200z4e200z4e 200z4e200z4 MaximumOperatingFrequency2160 MHz (z4)80 MHz (z2)160 MHz (z4)80 MHz (z2)160 MHz (z4)160 MHz (z4)80 MHz (z2)160 MHz (z4)160 MHz (z4)80 MHz (z2)160 MHz (z4)160 MHz (z4)80 MHz (z2)Flash memory4 MB6 MB3 MB4 MB6 MBEEPROM support32 KB to 128 KB emulated32 KB to 192 KB emulatedRAM512 KB768 KBECCEnd to EndSMPUSMPU_0: 12 entry, SMPU_1: 12 entrySMPU_0.

10 16 entry, SMPU_1: 16 entryDMA32 channels10-bit ADC48 Standard channels32 External channels12-bit ADC16 Precision channels16 Standard channels32 External channelsAnalogComparator3 BCTU1 SWT243 STM23 PIT-RTI16 channels PIT1 channels RTIRTC/APIYesTotal Timer I/O496 channels16-bitsLINFlexD1 M/S, 15 M1 M/S, 17 MFlexCAN8 with optional CAN FD supportDSPI/SPI4 x DSPI6 x SPIT able continues on the next comparisonMPC5748G Microcontroller Data Sheet , Rev. 6, 11/2018 NXP Semiconductors5 Table 1. MPC5748G Family Comparison1 (continued)FeatureMPC5747 CMPC5748 CMPC5746 GMPC5747 GMPC5748GI2C4 SAI/I2S3 FXOSC8 - 40 MHzSXOSC32 KHzFIRC16 MHzSIRC128 KHzFMPLLYesLPUYesFlexRay (dualchannel)Yes, 128 MBMLB15001 USB SPH01 USB OTG01 SDHC1 Ethernet (RMII, MII+ 1588, Muti queueAVB support)Up to 23 Port L2 EthernetSwitchOptionalCRC1 MEMU2 STCU1 HSM-v2 (security)OptionalCensorshipYesFCCU1 Safety levelSpecific functions ASIL-B certifiableUser MBISTYesUser LBISTYesI/O Retention inStandbyYesGPI17 (176 LQFP-EP), 18 (256 BGA), 18 (324 BGA)GPIO129 (176 LQFP-EP)