MX25L12833F - MXIC

MX25L12833F . MX25L12833F . 3V, 128M-BIT [x 1/x 2/x 4]. CMOS MXSMIO (SERIAL MULTI I/O). FLASH MEMORY. Key Features Protocol Support - Single I/O, Dual I/O and Quad I/O. Quad Peripheral Interface (QPI) available Support clock frequency up to 133 MHz Program/Erase Suspend and Resume Additional 8K-bit secured OTP. P/N: PM2517. MX25L12833F . Contents 1. 4. 2. GENERAL 5. Table 1. Read performance 3. PIN CONFIGURATIONS .. 6. 4. PIN 6. 5. BLOCK 7. 6. DATA 8. Table 2. Protected Area Table 3. 8K-bit Secured OTP 7. Memory 11. Table 4. Memory 11. 8. DEVICE 12. 8-1. Quad Peripheral Interface (QPI) Read 14. 9. COMMAND 15. Table 5. Command 9-1. Write Enable (WREN).. 18. 9-2. Write Disable (WRDI).. 19. 9-3. Factory Mode Enable (FMEN).. 20. 9-4. Read Identification (RDID).. 21. 9-5. Release from Deep Power-down (RDP), Read Electronic Signature (RES).. 22. 9-6. Read Electronic Manufacturer ID & Device ID (REMS).

RESET#/SIO3 SCLK SI/SIO0 8 7 6 5 Notes: The pin of RESET#, RESET#/SIO3 or WP#/SIO2 will remain internal pull up function while this pin is not physically connected in system configuration. However, the internal pull up function will be disabled if the system has physical connection to RESET#, RESET#/SIO3 or WP#/SIO2 pin. 16-PIN SOP (300mil) 1 2 ...

Loading..

Tags:

  Sio3

Information

Related search queries