MX25L12833F - MXIC

1 MX25L12833F . MX25L12833F . 3V, 128M-BIT [x 1/x 2/x 4]. CMOS MXSMIO (SERIAL MULTI I/O). FLASH MEMORY. Key Features Protocol Support - Single I/O, Dual I/O and Quad I/O. Quad Peripheral Interface (QPI) available Support clock frequency up to 133 MHz Program/Erase Suspend and Resume Additional 8K-bit secured OTP. P/N: PM2517. MX25L12833F . Contents 1. 4. 2. GENERAL 5. Table 1. Read performance 3. PIN CONFIGURATIONS .. 6. 4. PIN 6. 5. BLOCK 7. 6. DATA 8. Table 2. Protected Area Table 3. 8K-bit Secured OTP 7. Memory 11. Table 4. Memory 11. 8. DEVICE 12. 8-1. Quad Peripheral Interface (QPI) Read 14. 9. COMMAND 15. Table 5. Command 9-1. Write Enable (WREN).. 18. 9-2. Write Disable (WRDI).. 19. 9-3. Factory Mode Enable (FMEN).. 20. 9-4. Read Identification (RDID).. 21. 9-5. Release from Deep Power-down (RDP), Read Electronic Signature (RES).. 22. 9-6. Read Electronic Manufacturer ID & Device ID (REMS).

2 24. 9-7. QPI ID Read (QPIID).. 25. Table 6. ID Definitions ..25. 9-8. Read Status Register (RDSR).. 26. 9-9. Read Configuration Register (RDCR).. 27. Table 7. Status Table 8. Configuration Register Table 9. Output Driver Strength Table 10. Dummy Cycle and Frequency Table (MHz)..32. 9-10. Write Status Register (WRSR).. 33. Table 11. Protection 9-11. Read Data Bytes (READ).. 37. 9-12. Read Data Bytes at Higher Speed (FAST_READ).. 38. 9-13. Dual Output Read Mode (DREAD).. 39. 9-14. 2 x I/O Read Mode (2 READ).. 40. 9-15. Quad Read Mode (QREAD).. 41. 9-16. 4 x I/O Read Mode (4 READ).. 42. 9-17. Burst 44. 9-18. Performance Enhance 45. 9-19. Sector Erase (SE).. 48. 9-20. Block Erase (BE32K).. 49. 9-21. Block Erase (BE).. 50. 9-22. Chip Erase (CE).. 51. 9-23. Page Program (PP).. 52. P/N: PM2517 Rev. , October 17, 2017. 2. MX25L12833F . x I/O Page Program (4PP).. 54. Power-down (DP).

3 55. Secured OTP (ENSO).. 56. Secured OTP (EXSO).. 56. Security Register (RDSCUR).. 56. Security Register (WRSCUR).. 56. Table 12. Security Register 9-30. Write Protection Selection (WPSEL).. 58. 9-31. Advanced Sector 60. 9-32. Program/Erase 66. 9-33. Erase 66. 9-34. Program 66. 9-35. 68. 9-36. No Operation (NOP).. 68. 9-37. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).. 68. 9-38. Read SFDP Mode (RDSFDP).. 70. 10. 71. Table 13. Reset Timing-(Power On)..71. Table 14. Reset Timing-(Other Operation)..71. 11. POWER-ON 72. 12. ELECTRICAL 73. Table 15. ABSOLUTE MAXIMUM Table 16. CAPACITANCE TA = 25 C, f = Table 17. DC CHARACTERISTICS ..75. Table 18. AC CHARACTERISTICS ..76. 13. OPERATING 78. Table 19. Power-Up/Down Voltage and 13-1. INITIAL DELIVERY 80. 14. ERASE AND PROGRAMMING 81. 15. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode) .. 81. 16. DATA 82. 17.

4 LATCH-UP 82. 18. ORDERING 83. 19. PART NAME 84. 20. PACKAGE 85. 20-1. 8-pin SOP (200mil).. 85. 20-2. 16-pin SOP (300mil).. 86. 20-3. 8-land WSON (6x5mm).. 87. 20-4. 8-land WSON (8x6mm).. 88. 21. REVISION HISTORY .. 89. P/N: PM2517 Rev. , October 17, 2017. 3. MX25L12833F . 3V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O). FLASH MEMORY. 1. FEATURES. GENERAL Command Reset Supports Serial Peripheral Interface -- Mode 0 and Program/Erase Suspend and Resume operation Mode 3 Electronic Identification Single Power Supply Operation - JEDEC 1-byte manufacturer ID and 2-byte device - to volt for read, erase, and program ID. operations - RES command for 1-byte Device ID. 134,217,728 x 1 bit structure - REMS command for 1-byte manufacturer ID and or 67,108,864 x 2 bits (two I/O mode) structure 1-byte device ID. or 33,554,432 x 4 bits (four I/O mode) structure Support Serial Flash Discoverable Parameters Protocol Support (SFDP) mode - Single I/O, Dual I/O and Quad I/O.

5 Latch-up protected to 100mA from -1V to Vcc +1V HARDWARE FEATURES. Fast read for SPI mode SCLK Input - Support clock frequency up to 133 MHz for all - Serial clock input protocols SI/SIO0. - Support Fast Read, 2 READ, DREAD, 4 READ, - Serial Data Input or Serial Data Input/Output for 2. QREAD instructions. x I/O read mode and 4 x I/O read mode - Configurable dummy cycle number for fast read SO/SIO1. operation - Serial Data Output or Serial Data Input/Output for Quad Peripheral Interface (QPI) available 2 x I/O read mode and 4 x I/O read mode Equal Sectors with 4K byte each, or Equal Blocks WP#/SIO2. with 32K byte each or Equal Blocks with 64K byte - Hardware write protection or serial data Input/Out- each put for 4 x I/O read mode - Any Block can be erased individually RESET# (16-pin package). Programming : - Hardware Reset pin - 256byte page buffer RESET#/ sio3 .

6 - Quad Input/Output page program(4PP) to enhance - Hardware Reset pin or Serial input & Output for 4. program performance x I/O read mode Typical 100,000 erase/program cycles PACKAGE. 20 years data retention -8-pin SOP (200mil). -16-pin SOP (300mil). SOFTWARE FEATURES -8-land WSON (6x5mm). Input Data Format -8-land WSON (8X6mm). - 1-byte Command code - All devices are RoHS Compliant and Halogen- Advanced Security Features free - Block lock protection The BP0-BP3 and T/B status bit defines the size of the area to be protection against program and erase instructions - Advanced sector protection function (Solid Protect). Additional 8K bit security OTP. - Features unique identifier - Factory locked identifiable, and customer lockable P/N: PM2517 Rev. , October 17, 2017. 4. MX25L12833F . 2. GENERAL DESCRIPTION. MX25L12833F is 128Mb bits Serial NOR Flash memory, which is configured as 16,777,216 x 8 internally.

7 When it is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. MX25L12833F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O. mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits in- put and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin (of the 8-pin pack- ages) become SIO0 pin, SIO1 pin, SIO2 pin and sio3 pin for address/dummy bits input and data output. The MX25L12833F MXSMIO (Serial Multi I/O) provides sequential read operation on the whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci- fied page or sector/block locations will be executed.

8 Program command is executed on byte basis, or page (256. bytes) basis, or word basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it will remain in standby mode. The MX25L12833F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Table 1. Read performance Comparison Dual Output Quad Output Dual IO Quad IO. Numbers of Fast Read Fast Read Fast Read Fast Read Fast Read Dummy Cycles (MHz).

9 (MHz) (MHz) (MHz) (MHz). 4 - - - 84* 66. 6 104 104 84 104 84*. 8 104* 104* 104* 104 104. 10 133 133 133 133 120/133R. Notes: 1. * mean default status. 2. R mean VCC range = P/N: PM2517 Rev. , October 17, 2017. 5. MX25L12833F . 3. PIN CONFIGURATIONS 4. PIN DESCRIPTION. 8-PIN SOP (200mil) SYMBOL DESCRIPTION. CS# Chip Select CS# 1 VCC. SO/SIO1 2. 8. 7 RESET#/ sio3 . Serial Data Input (for 1 x I/O)/ Serial WP#/SIO2 3 6 SCLK SI/SIO0 Data Input & Output (for 2xI/O or 4xI/O. GND 4 5 SI/SIO0 read mode). Serial Data Output (for 1 x I/O)/ Serial SO/SIO1 Data Input & Output (for 2xI/O or 4xI/O. read mode). 16-PIN SOP (300mil) SCLK Clock Input Write protection Active low or Serial DNU/ sio3 1 16 SCLK. VCC 2 15 SI/SIO0. WP#/SIO2 Data Input & Output (for 4xI/O read RESET# 3 14 NC mode). NC 4 13 NC. NC 5 12 NC. Hardware Reset Pin Active low or NC 6 11 NC RESET#/ sio3 Serial Data Input & Output (for 4xI/O.)

10 CS# 7 10 GND. read mode). SO/SIO1 8 9 WP#/SIO2. RESET# Hardware Reset Pin Active low VCC + 3V Power Supply GND Ground 8-WSON (6x5mm, 8x6mm) NC No Connection DNU Do not use CS# 1 8 VCC Notes: SO/SIO1 2 7 RESET#/ sio3 The pin of RESET#, RESET#/ sio3 or WP#/SIO2 will WP#/SIO2 3 6 SCLK remain internal pull up function while this pin is not GND 4 5 SI/SIO0 physically connected in system configuration. However, the internal pull up function will be disabled if the system has physical connection to RESET#, RESET#/ sio3 or WP#/SIO2 pin. P/N: PM2517 Rev. , October 17, 2017. 6. MX25L12833F . 5. BLOCK DIAGRAM. X-Decoder Address Memory Array Generator SI/SIO0. Y-Decoder SO/SIO1. SIO2 * Data sio3 * Register WP# *. SRAM Sense HOLD# * Buffer Amplifier RESET# *. CS#. Mode State HV. Logic Machine Generator SCLK Clock Generator Output Buffer * Depends on part number options. P/N: PM2517 Rev.