Transcription of NOVEMBER 2009 3.3V ECL Differential …
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NOVEMBER 2009 3.3V ECL Differential …
SN65 EPT23. SLLS969A NOVEMBER 2009 REVISED JANUARY 2011. ECL Differential lvpecl / lvds to lvttl / lvcmos translator Check for Samples: SN65 EPT23. 1 FEATURES. Dual V Differential lvpecl / lvds to PINOUT ASSIGNMENT. lvttl / lvcmos Buffer translator + +. 24 mA lvttl Ouputs D0 1 8 VCC. Operating Range +. VCC = V to V. GND = 0 V D0 2 7 Q0. lvpecl lvttl . Support for Clock Frequencies > 300 MHz +. ns Typical Propagation Delay D1 3 6 Q1. Built-in Temperature Compensation +. Drop in Compatible to MC100 EPT23. D1 4 5 GND. APPLICATIONS. Data and Clock Transmission Over Backplane Table 1. Pin Description Signaling Level Conversion for Clock or Data PIN FUNCTION. DESCRIPTION Q0, Q1 lvttl / lvcmos Outputs D0, D 0, D1, D 1 Differential lvpecl / lvds /CML Inputs The SN65 EPT23 is a low power dual lvpecl / lvds . to lvttl / lvcmos translator device. The device VCC Positive Supply includes circuitry to maintain inputs at Vcc/2 when left GND Ground open. The SN65 EPT23 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 option.
1 8 2 7 3 6 4 5 D0 Q0 Q1 V CC D0 D1 D1 GND LVPECL LVTTL + + + + + SN65EPT23 www.ti.com SLLS969A –NOVEMBER 2009–REVISED JANUARY 2011 3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator
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