NVIDIA Fermi Architecture Whitepaper

Whitepaper NVIDIA s Next Generation CUDATM Compute Architecture : FermiTM Table of ContentsTable of ContentsTable of ContentsTable of Contents A Brief History of GPU Computing ..3 The G80 Architecture ..4 NVIDIA s Next Generation CUDA Compute and Graphics Architecture , Code-Named Fermi ..4 A Quick Refresher on CUDA ..6 Hardware Execution ..7 An Overview of the Fermi Architecture ..7 Third Generation Streaming Multiprocessor ..8 512 High Performance CUDA cores ..8 16 Load/Store Units ..8 Four Special Function Units ..9 Designed for Double Precision ..9 Dual Warp Scheduler ..10 64 KB Configurable Shared Memory and L1 Cache ..10 Summary Table ..11 Second Generation Parallel Thread Execution ISA.

point unit (FPU). Prior GPUs used IEEE 754-1985 floating point arithmetic. The Fermi architecture implements the new IEEE 754-2008 floating-point standard, providing the fused multiply-add (FMA) instruction for both single and double precision arithmetic. FMA improves over a multiply-add (MAD) instruction by doing the multiplication and

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