Transcription of NVMe performance optimization and stress testing
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NVMe performance optimization and stress testing
nvme performance optimization and stress testing Isaac Livny Teledyne Corporation Santa Clara, CA August 2017 1 Agenda nvme / NVMoF transfer overview PCIe perforamce analysis NVMoF over CNA example nvme performance analysis LBA distribution analysis Conditional performance analysis using scripting stress testing using traffic generation Script examples Santa Clara, CA August 2017 2 nvme complete transfer Santa Clara, CA August 2017 3 Host Submission Queue Tail Doorbell . Queue Process Completion Completion Queue Head Doorbell nvme Controller Tail Head Head Tail Host Memory Submission Queue Completion Queue Ring Doorbell New Head Process Completion Queue Command Ring Doorbell New Tail PCIe TLP PCIe TLP .. PCIe TLP PCIe TLP PCIe TLP .. PCIe TLP Fetch Command Process Command Queue Completion Generate Interrupt 1 2 3 4 5 6 7 8 PCIe TLP PCIe TLP PCIe TLP PCIe TLP PCIe TLP PCIe TLP PRP / SGL Each PRP data line in nvme transaction view corresponds to pointer in a PRP list SGL descriptor types 8/16/17 5 SGL descriptor SGL descriptor (1) command line, indicating the first SGL segment for the command and decoding its fields.
NVMe performance optimization and stress testing Isaac Livny Teledyne Corporation Santa Clara, CA August 2017 1
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