Transcription of OMAP-L138 C6000™ DSP+ ARM Processor - TI.com
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OMAP-L138 C6000™ DSP+ ARM Processor - TI.com
Product Order Technical Tools & Support &. Folder Now Documents Software Community OMAP-L138 . SPRS586J JUNE 2009 REVISED JANUARY 2017. OMAP-L138 C6000 DSP+ ARM Processor 1 Device Overview 1. Features Dual-Core SoC Supports 32-Bit Integer, SP (IEEE Single 375- and 456-MHz ARM926EJ-S RISC MPU Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point 375- and 456-MHz C674x Fixed- and Floating- Point VLIW DSP Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks ARM926EJ-S Core Supports up to Two Floating-Point (SP or DP). 32- and 16-Bit (Thumb ) Instructions Reciprocal Approximation (RCPxP) and DSP Instruction Extensions Square-Root Reciprocal Approximation Single-Cycle MAC (RSQRxP) Operations Per Cycle ARM Jazelle Technology Two Multiply Functional Units: Embedded ICE-RT for Real-Time Debug Mixed-Precision IEEE Floating-Point Multiply ARM9 Memory Architecture Supported up to: 16KB of Instruction Cache 2 SP SP SP Per Clock 16KB of Data Cache 2 SP SP DP Every Two Clocks 8KB of RAM (Vector Table) 2 SP DP DP Every Three Clocks 64KB of ROM 2 DP DP DP Every Four Clocks C674x Instruction Set Features Fixed-Point Multiply Supports Two 32 32- Superset of the C67x+ and C64x+ ISAs Bit Multiplies, Four 16 16-Bit Multiplies, or Up to 3648 MIPS and 2746 MFLOPS Eight 8 8-Bit Multiplies per Clock Cycle, Byte-Address
Product Folder Order Now Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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