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PCIe 3.1 & M-PCIe™ Protocol

Copyright 2014, PCI-SIG, All Rights ReservedPCIe & M-PCIe ProtocolRichard SolomonSynopsys1 PCIeTechnology SeminarCopyright 2014, PCI-SIG, All Rights ReservedDisclaimerThe information in this presentation refers to specifications still in the development process. This presentation reflects the current thinking of various PCI-SIG workgroups, but all material is subject to change before the specifications are released. 2 PCIeTechnology SeminarAgenda PCIe Base Spec Newer Protocol ECNs Protocol ECRs Under Development M-PCIe ECNC opyright 2014, PCI-SIG, All Rights Reserved3 PCIeTechnology SeminarCopyright 2014, PCI-SIG, All Rights ReservedProtocol Content IncludedIn the PCIe Base Spec Older Protocol ECNs Against the PCIe Base Spec (not covered here) Process Address Space ID (PASID) Receiver Impedance Lightweight Notification (LN) Protocol Downstream Port Conta

Retimer (protocol aware) Limited LTSSM device with no config space that drops out of the protocol after participating in TX EQ negotiation (end of phase 3) Supports a full PCIe 3.0 Base Spec worst case channel in both directions Re-driver Does not participate in TX EQ negotiation Lower latency, lower active power

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