Transcription of Phase-Locked Loop Design Fundamentals
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Phase-Locked Loop Design Fundamentals
Freescale Semiconductor, Inc., 1994, 2006. All rights SemiconductorApplication NoteDocument Number: AN535 Rev. , 02/2006 AbstractThe fundamental Design concepts for Phase-Locked loops implemented with integrated circuits are outlined. The necessary equations required to evaluate the basic loop performance are given in conjunction with a brief Design document contains references to obsolete part numbers and is offered for technical information purpose of this application note is to provide the electronic system designer with the necessary tools to Design and evaluate Phase-Locked loops (PLL) configured with integrated circuits. The majority of all PLL Design problems can be approached using the Laplace Transform technique. Therefore, a brief review of Laplace is included to establish a common reference Phase-Locked Loop Design Fundamentalsby: Garth NashApplications EngineeringContents1 Introduction.
Phase-Locked Loop Design Fundamentals Application Note, Rev. 1.0 Freescale Semiconductor 7 Example: The root locus for a typical loop transfer function is found as follows: Eqn. 26 The root locus has two branches (Rul e 2) which begin at s = 0 and s = -4 and ends at the two zeroes located at infinity (Rule 1).
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