Transcription of R XC2C64A CoolRunner-II CPLD
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DS311 ( ) November 19, Specification 2004 2008 xilinx , Inc. All xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without Optimized for systems-As fast as ns pin-to-pin logic delays -As low as 15 A quiescent current Industry s best micron CMOS CPLD -Optimized architecture for effective logic synthesis-Multi-voltage I/O operation to Available in multiple package options-44-pin VQFP with 33 user I/Os-48-land QFN with 37 user I/Os-56-ball CP BGA with 45 user I/Os-100-pin VQFP with 64 user I/Os-Pb-free available for all packages Advanced system features-Fastest in system programming ISP using IEEE 1532 (JTAG) JTAG Boundary Scan Test-Optional Schmitt-trigger input (per pin)
XC2C64A CoolRunner-II CPLD 4 www.xilinx.com DS311 (v2.3) November 19, 2008 Product Specification R LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications LVCMOS 2.5V DC Voltage Specifications LVCMOS 1.8V DC Voltage Specifications
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