RISC-V ASSEMBLY LANGUAGE Programmer Manual Part I

RISC-V ASSEMBLYLANGUAGEP rogrammer ManualPart Ideveloped by: SHAKTI Development Team @ iitm @ Proprietary NoticeCopyrightc 2020,Shakti @ IIT rights reserved. Information in this document is provided as is , with all @ IIT Madrasexpressly disclaims all warranties, representations, and conditions ofany kind, whether express or implied, including, but not limited to, the implied warranties orconditions of merchant ability, fitness for a particular purpose and @ IIT Madrasdoes not assume any liability rising out of the application or use of anyproduct or circuit, and specifically disclaims any and all liability, including without limitationindirect, incidental, special, exemplary.

PART-I of the RISC-V programmer’s manual, details RISC-V assembly instructions, registers in use and the machine privilege level. Advanced concepts on Privilege levels, Memory Management unit and Trap delegation will be dealt with in PART-II of the manual. The objective of the RISC-V ASM (assembly language) programmer manual is to aid users in

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