RISC-V ASSEMBLY LANGUAGE Programmer Manual Part I

1 RISC-V ASSEMBLYLANGUAGEP rogrammer ManualPart Ideveloped by: SHAKTI Development Team @ iitm @ Proprietary NoticeCopyrightc 2020,Shakti @ IIT rights reserved. Information in this document is provided as is , with all @ IIT Madrasexpressly disclaims all warranties, representations, and conditions ofany kind, whether express or implied, including, but not limited to, the implied warranties orconditions of merchant ability, fitness for a particular purpose and @ IIT Madrasdoes not assume any liability rising out of the application or use of anyproduct or circuit, and specifically disclaims any and all liability, including without limitationindirect, incidental, special, exemplary.

2 Or consequential @ IIT Madrasreserves the right to make changes without further notice to any Release 12, 2020 Initial 07, 2020 Updates and adding new 14, 2021 Update MUL descriptions for unsignedTable of Notice .. Information ..3 List of Figures7 List of Tables81 RISC-V .. Registers .. Pointer Register .. Pointer Register .. Pointer Register .. Address Register .. Register .. Register .. Privilege mode .. Control and Status Registers (CSRs) .. Field Specifications .. CSR Instructions .. to Register instructions .. Instructions.

3 Information Registers ..202 Load and Store RV 32I .. Instructions .. instructions .. RV 64I .. Instructions .. Pseudo Instructions .. pseudo instructions ..373 Bitwise RV 32I .. to Register Instructions .. instructions .. RV 64I .. to Register Instructions .. instructions ..534 Arithmetic RV 32I .. to Register instructions .. Instructions .. RV 64I .. to Register instructions .. Word Instructions ..665 Control Transfer Branch Instructions .. Instructions .. Unconditional Jump Instructions .. System Instructions.

4 806 Trap s in Exceptions .. Instruction Exception .. Address Misaligned Exception .. Address Misaligned Exception .. Address Misaligned Exception .. Access Fault .. Access Fault .. Access Fault .. Point .. Call .. Handling Exceptions .. Handling Registers .. Understanding Stack in RISC-V ..907 Timer Interrupts .. Register .. Register .. Interrupt flow chart .. External Interrupts .. Software Interrupts ..958 Assembler Object File section .. Functions ..FILE ..IDENT ..SIZE .. Directives for Definition and Exporting of symbols.

5 Alignment Control .. Assembler Directives for Emitting Data .. 1089 Example Programs and Practice Important Prerequisites .. ASSEMBLY LANGUAGE Example Programs .. Transfer Instructions .. Instructions .. Operations - Illustrating various logical operations with immedi-ate values and between contents of registers .. Operations - Illustrating conditional operations between con-tents of registers .. 122 List of Machine ISA Register (misa) .. Machine VendorID register (mvendorid) .. Machine Architecture ID Register (marchid).

6 Machine Implementation ID Register (mimpid).. Hart ID Register (mhartid).. Machine-Mode Status Register (mstatus) for RV64 .. Machine-Mode Status Register (mstatus) for RV32.. Machine Cause Register (mcause).. Machine Trap-Vector Base-Address Register (mtvec) .. Machine Exception Program Counter Register (mepc).. Standard portion (bits 15:0) ofmie.. Standard portion (bits 15:0) ofMIP.. Machine Trap Value register (mtval).. Machine-mode scratch Register (mscratch).. Trap occurrence and handling mechanism .. Exception handling part .. Machine-mode status register (mstatus) for RV64.

7 Machine-mode status register (mstatus) for RV32..907 List of Tables1 List Of Abbreviations .. RISC-V Base Integer Registers Of Size XLEN .. RISC-V Privilege Levels .. RISC-V Machine Mode Registers.. RISC-V ISA extensions .. Basic Commands and Usage with misa Register .. Basic Commands and Usage with mvendorid Register .. Basic Commands and Usage with marchid Register .. Basic Commands and Usage with mimpid Register .. Basic Commands and Usage with mhartid Register .. Basic Commands and Usage with mstatus Register .. Machine cause register (mcause) values after trap.

8 Basic Commands and Usage with mcause Register .. Encoding ofmtvecMODE field.. Basic Commands and Usage with mtvec Register .. Basic Commands and Usage with mepc Register .. Basic Commands and Usage MIE Register .. Basic Commands and Usage with MIP Register .. Basic Commands and Usage with mtval Register .. Basic Commands and Usage with mscratch Register ..2889 CSRC ontrol and Status RegisterGPGlobal PointerHARTH ardware ThreadIMMI mmediate DataISAI nstruction Set ArchitectureMARCHIDM achine Architecture IDMCAUSETrap cause code, Machine ModeMCOUNTERENC ounter enable, Machine ModeMCYCLEC lock cycle counter, Machine ModeMEIPM achine external interruptMEPCM achine Exception Program counterMHARTIDH ardware thread IDMIEI nterrupt-enable register, Machine ModeMIMPIDI mplementation IDMIPI nterrupt pending, Machine ModeMISAISA and extensionsMSTATUSS tatus register, Machine ModeMTIPM achine timer interruptMTVALBad address or bad instruction.

9 Machine ModeMTVECM achine Trap Vector base addressMVENDORIDM achine Mode Vendor IDNANot ApplicableNMINon Maskable InterruptRISCR educed Instruction Set ComputerRV128 / RV128 IInstructions present only on 128 bit machinesRV64 / RV64 IInstructions present only on 64 and 128 bit machinesRV32 / RV32 IBasic 32 bit instruction set, present on all machinesSPStack PointerTPThread PointerXLENI nstruction (X) 1: List Of RISC-VRISC-V pronounced as RISC-five , is an open-source standard Instruction Set Architecture (ISA),designed based on Reduced Instruction Set Computer (RISC) principles. With a flexible architectureto build systems ranging from a simple microprocessor to complex multi-core systems, RISC-V catersto any market.

10 The RISC-V ISA provides two specifications, one, the User Level Instructions whichguides in developing simple embedded systems and connectivity applications and two, the PrivilegeLevel Instructions which guides in building secure systems, kernel, and protected software currently supports three privilege levels, Machine/Supervisor/User, with each levelhaving dedicated Control Status Registers (CSRs) for system state observation and addition, RISC-V provides 31 read/write registers. While all can be used as general-purposeregisters, they have dedicated functions as well. RISC-V is divided into different categories basedon the maximum width of registers the architecture can support, for example, RV32 ( RISC-V 32)provides registers whose maximum width is 32-bits and RV64 ( RISC-V 64) provides registers whosemaximum width is 64-bits.