Transcription of Section 5 High Speed PCB Layout Techniques - TI.com
{{id}} {{{paragraph}}}
Example: tourism industry
Section 5 High Speed PCB Layout Techniques - TI.com
high Speed Analog Design and Application Seminar5-1 texas InstrumentsSection 5 high Speed PCB Layout TechniquesScenario: You have spent several days, no maybe weeks, perfecting adesign on paper and also using Spice to ensure the design exceeds allexpectations. You hand the schematic to your Layout person who puts alleverything on a printed circuit board (PCB). The PCB comes back in a weekor two and is finally populated and ready to test. But it doesn t work!!!!Why not? On paper it works!! Spice said it works!! But it doesn t work!!This scenario happens more often than not and the reason many circuits donot work as expected is due primarily to the PCB Section looks at some key fundamentals of high Speed PCB layouttechniques so that hopefully the above scenario will never happen to Speed Analog Design and Application Seminar5-2 texas InstrumentsPCB Components + twhlnL(nH) () ++ twhlnrC(pF) htw rComponent: Copper TracesPurpose: Interconnect two or more pointsProblem: Inductance and Capacitancex = length of trace (cm)w = width of trace (cm)h = height of trace (cm)t = thickness of trace (cm)er = PCB ( ) trace on ( ) thick PCB (FR-4) has: 4nH and per cm 10nH and per inchL(nH)C(pF))ps/cm( ()C(pF)L(nH) er = PCB materialpermeability (FR-4 )The PCB consists o
High Speed Analog Design and Application Seminar 5-4 Texas Instruments 0.4mm (0.0157”) via with 1.6mm (0.063”) thick PCB has ˜ 1.2nH 1.6mm (0.063”) Clearance hole around 0.8mm (0.031”) pad on FR-4 has ˜ 0.4pF Component: Vias
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: