Transcription of SEMICONDUCTOR MEMORIES
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SEMICONDUCTOR MEMORIES
Digital Integrated Circuits Prentice Hall 1995 MemorySEMICONDUCTORMEMORIESD igital Integrated Circuits Prentice Hall 1995 MemoryChapter Overview Memory Classification Memory Architectures The Memory Core Periphery ReliabilityDigital Integrated Circuits Prentice Hall 1995 MemorySemiconductor MemoryClassificationRWMNVRWMROMEPROME2 PROMFLASHR andomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOS hift RegisterCAMLIFOD igital Integrated Circuits Prentice Hall 1995 MemoryMemory Architecture: DecodersWord 0 Word 1 Word 2 Word N-1 Word N-2 Input-OutputS0S1S2SN-2SN_1(M bits)StorageCellM bitsN WordsWord 0 Word 1 Word 2 Word N-1 Word N-2 Input-Output(M bits)StorageCellM bitsDecoderA0A1AK-1S0N words => N select signalsToo many select signalsDecoder reduces # of select signalsK = log2 NDigital Integrated Circuits Prentice Hall 1995 MemoryArray-Structured Memory ArchitectureInput-Output(M bits)Row DecoderAKAK+1AL-12L-KColumn DecoderBit LineWord LineA0AK-1 Storage CellSense Amplifiers / : ASPECT RATIO or HEIGHT >> WIDTHA mplify swing torail-to-rai
The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a “1” into a DRAM cell, a threshold voltage is lost.
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