SEMICONDUCTOR MEMORIES
Digital Integrated Circuits Prentice Hall 1995MemorySEMICONDUCTORMEMORIESDigital Integrated Circuits Prentice Hall 1995MemoryChapter Overview Memory Classification Memory Architectures The Memory Core Periphery ReliabilityDigital Integrated Circuits Prentice Hall 1995MemorySemiconductor MemoryClassificationRWMNVRWMROMEPROME2PR OMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOShift RegisterCAMLIFODigital Integrated Circuits Prentice Hall 1995MemoryMemory Architecture: DecodersWord 0Word 1Word 2Word N-1Word N-2Input-OutputS0S1S2SN-2SN_1(M bits)StorageCellM bitsN WordsWord 0Word 1Word 2Word N-1Word N-2Input-Output(M bits)StorageCellM bitsDecoderA0A1AK-1S0N words => N select signalsToo many select signalsDecoder reduces # of select signalsK = log2NDigital Integrated Circuits Prentice Hall 1995MemoryArray-Structured Memory ArchitectureInput-Output(M bits)Row DecoderAKAK+1AL-12L-KColumn DecoderBit LineWord LineA0AK-1Storage CellSense Amplifiers / : ASPECT RATIO or HEIGHT >> WIDTHAmplify swing torail-to-rail amplitudeSelects appr
The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a “1” into a DRAM cell, a threshold voltage is lost.
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