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Semiconductor Packing Material Electrostatic …
Application ReportSZZA047 - July 20041 Semiconductor Packing MaterialElectrostatic discharge (ESD) ProtectionAlbert Escusa and Lance WrightStandard Linear and LogicABSTRACTF orty-eight-pin TSSOP components that were packaged using Texas Instruments (TI)standard Packing methodology were subjected to electrical discharges between and 20kV, as generated by an IEC ESD simulator to determine the level of ESD protection providedby the Packing materials. The testing included trays, tape and reel, and units were subjected to the same discharge , without the protection of the packingmaterial. Test results showed that the Packing materials used by TI provide protection up to20 kV, and that a level of ESD protection is required. The die in the components had a ChargeDevice Model (CDM) rating of kV, and all units experiencing a discharge greater than 500V sustained sufficient electrical overstress to fail electrical testing when outside of the .. 2 Packing Methods3.
Application Report SZZA047 - July 2004 1 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Albert …
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