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Semiconductor Packing Material Electrostatic …
Application ReportSZZA047 - July 20041 Semiconductor Packing MaterialElectrostatic discharge (ESD) ProtectionAlbert Escusa and Lance WrightStandard Linear and LogicABSTRACTF orty-eight-pin TSSOP components that were packaged using Texas Instruments (TI)standard Packing methodology were subjected to electrical discharges between and 20kV, as generated by an IEC ESD simulator to determine the level of ESD protection providedby the Packing materials. The testing included trays, tape and reel, and units were subjected to the same discharge , without the protection of the packingmaterial.
Application Report SZZA047 - July 2004 1 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Albert …
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