Transcription of Serial LVDS High-Speed ADC Interface - Xilinx
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Serial LVDS High-Speed ADC Interface - Xilinx
XAPP524 ( ) November 20, 1 Copyright 2012 Xilinx , Inc. Xilinx , the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective application note describes a method of utilizing dedicated SelectIO technology deserializer components (ISERDESE2 primitives) in 7 series FPGAs to Interface with analog -to- digital converters (ADC) with Serial , low-voltage, differential signalling (LVDS)
Figure 3 shows the analog input signal along with the input, bit, and frame clocks. Sample N of the analog signal is converted to digital format and presented at the ADC outputs after a latency period. The analog signal is converted into a digital, serial data stream with 12-bit ADC resolution that is provided together
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