Transcription of Serial LVDS High-Speed ADC Interface - Xilinx
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Serial LVDS High-Speed ADC Interface - Xilinx
XAPP524 ( ) November 20, 1 Copyright 2012 Xilinx , Inc. Xilinx , the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective application note describes a method of utilizing dedicated SelectIO technology deserializer components (ISERDESE2 primitives) in 7 series FPGAs to Interface with analog-to-digital converters (ADC) with Serial , low-voltage, differential signalling (LVDS) associated reference design illustrates a basic LVDS Interface connecting a Kintex -7 FPGA to an ADC with High-Speed , Serial LVDS High-Speed ADCs used today have a resolution of 12, 14, or 16 bits with possible multiple converters in a single package.
LVDS channel with either the most-significant bit (MSB) or the least-significant bit (LSB) first and arranged with bit or byte alignment. The 1-wire interface encounters speed problems sooner than the 2-wire interface. In 1-wire mode, the reference design supports ADC resolutions up to 16 bits with sampling rates up to approximately 85 Ms/s.
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