Transcription of Serial Peripheral Interface (SPI) for KeyStone Devices ...
{{id}} {{{paragraph}}}
KeyStone architecture Literature Number: SPRUGP2 AMarch 2012 Serial Peripheral Interface (SPI)User guide -iiKeyStone architecture Serial Peripheral Interface (SPI) User GuideSPRUGP2A March Documentation Feedback Release HistoryReleaseDateDescription/CommentsAM arch 2010 Updated SCSFUN field description in SPIPC0 register from two pins to multiple pins (Page 3-9)Updated description as CSHOLD bit is 0 in Chip Select Hold Option section (Page 2-6)Updated the description of CSDEF field in SPIDEF register (Page 3-16)Updated the description of CSHOLD field in SPIDAT1 register (Page 3-11)Updated the description of CSNR field in SPIDAT1 register (Page 3-11)Updated the slave chip select pins number from 2 to n, which is device specific (Page 1-2)Modified the description of CSNR field in the SPIDAT1 register. (Page 3-11)SPRUGP2 November 2010 Initial ReleaseContentsSPRUGP2A March 2012 KeyStone architecture Serial Peripheral Interface (SPI) User guide -iiiSubmit Documentation Feedback History.
ø-ii KeyStone Architecture Serial Peripheral Interface (SPI) User Guide SPRUGP2A—March 2012 www.ti.com Submit Documentation Feedback Release History
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document:
{{id}} {{{paragraph}}}
CORE Architecture Definition Guide, Architecture Definition Guide, Definition, Guide, Architecture, Enterprise Architecture: Practical Guide to, Enterprise Architecture as Business Capabilities Architecture, Organizational architecture, OPENSTACK INTRODUCTION AND ARCHITECTURE, Transactive Energy, Ieee-1471