Transcription of SHARC+ Dual-Core DSP with Arm Cortex-A5 - Analog …
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SHARC+ Dual-Core DSP with Arm Cortex-A5 - Analog …
SHARC+ Dual-Core DSP with Arm Cortex-A5 . ADSP-SC582/SC583/SC584/SC587/SC589/ADSP- 21583/21584/21587. SYSTEM FEATURES 19 mm 19 mm 349/529 BGA ( pitch), RoHS compliant dual enhanced SHARC+ high performance floating-point Low system power across automotive temperature range cores MEMORY. Up to 500 MHz per SHARC+ core Large on-chip L2 SRAM with ECC protection, up to 256 kB. Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core On-chip L2 ROM (512 kB). with parity (optional ability to configure as cache). Two Level 3 (L3) interfaces optimized for low system power, 32-bit, 40-bit, and 64-bit floating-point support providing a 16-bit interface to DDR3 (supporting V. 32-bit fixed point capable DDR3L devices ), DDR2, or LPDDR1 SDRAM devices Byte, short-word, word, long-word addressed ADDITIONAL FEATURES.
SHARC® family of products. The ADSP-SC58x processor is based on the SHARC+ dual core and the Arm® Cortex®-A5 core. The ADSP-SC58x/ADSP-2158x SHARC processors are members of the SIMD SHARC family of digital signal proces-sors (DSPs) that feature Analog Devices, Inc., Super Harvard Architecture®. These 32-bit/40-bit/64-bit floating-point proces-
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