SHARC+ Dual-Core DSP with Arm Cortex-A5 - Analog …

1 SHARC+ Dual-Core DSP with Arm Cortex-A5 . ADSP-SC582/SC583/SC584/SC587/SC589/ADSP- 21583/21584/21587. SYSTEM FEATURES 19 mm 19 mm 349/529 BGA ( pitch), RoHS compliant dual enhanced SHARC+ high performance floating-point Low system power across automotive temperature range cores MEMORY. Up to 500 MHz per SHARC+ core Large on-chip L2 SRAM with ECC protection, up to 256 kB. Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core On-chip L2 ROM (512 kB). with parity (optional ability to configure as cache). Two Level 3 (L3) interfaces optimized for low system power, 32-bit, 40-bit, and 64-bit floating-point support providing a 16-bit interface to DDR3 (supporting V. 32-bit fixed point capable DDR3L devices ), DDR2, or LPDDR1 SDRAM devices Byte, short-word, word, long-word addressed ADDITIONAL FEATURES.

2 Arm Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle Security and Protection 32 kB L1 instruction cache/32 kB L1 data cache Cryptographic hardware accelerators 256 kB Level 2 (L2) cache with parity Fast secure boot with IP protection Powerful DMA system Support for Arm TrustZone On-chip memory protection Accelerators Integrated safety features High performance pipelined FFT/IFFT engine FIR, IIR, HAE, SINC offload engines AEC-Q100 qualified for automotive applications SYSTEM CONTROL PERIPHERALS. signal ROUTING UNIT (SRU). SECURITY AND PROTECTION. 2 2 PRECISION CLOCK. SYSTEM PROTECTION (SPU) core 0 core 1 core 2 GENERATORS. 2x DAI. SYSTEM MEMORY ASRC FULL SPORT 2x PIN.

3 PROTECTION UNIT (SMPU). FAULT MANAGEMENT. Arm .. Cortex-A5 . S S 2 4 PAIRS 2 4. 2 1 S/PDIF Rx/Tx BUFFER 40 28. Arm TrustZone SECURITY. 2. 3 I C. dual CRC L1 CACHE 6. 32 kB L1 I-CACHE L1 SRAM (PARITY) L1 SRAM (PARITY) 2 LINK PORTS. WATCHDOGS 32 kB L1 D-CACHE. 2 SPI + 1 QUAD SPI. OTP MEMORY 5 Mb (640 kB) 5 Mb (640 kB). L2 CACHE SRAM/CACHE SRAM/CACHE 3 UARTs THERMAL MONITOR UNIT (TMU) 256 kB (PARITY). 1 EPPI. PROGRAM FLOW 3 ePWM. SYS EVENT core 0 (GIC). 8 TIMERS + 1 COUNTER. SYS EVENT CORES 1-2 (SEC) G. SYSTEM CROSSBAR AND DMA SUBSYSTEM ADC CONTROL MODULE P. TRIGGER ROUTING (TRU) (ACM) I. O 102 80. ASYNC MEMORY (16-BIT). CLOCK, RESET, AND POWER. 2 CLOCK GENERATION (CGU).

4 SD/SDIO/eMMC. CLOCK DISTRIBUTION L3 MEMORY SYSTEM SYSTEM. UNIT (CDU) INTERFACES L2 MEMORY ACCELERATION MLB 3-PIN. REAL TIME CLOCK (RTC) DDR3 DDR3 SRAM DSP FUNCTIONS 2 EMAC. ROM ROM. DDR2 DDR2 (ECC) (FFT/IFFT, FIR, IIR, HAE/SINC). RESET CONTROL (RCU) 2 Mb 2 Mb SINC FILTER. LPDDR1 LPDDR1 2 Mb (256 kB) (256 kB). (256 kB) ENCRYPTION/DECRYPTION 8x SHARC FLAGS. POWER MANAGEMENT (DPM) 10. 16 16 2 USB HS. DEBUG UNIT 6. DATA DATA MLB 6-PIN. Arm CoreSightTM 7. (1 lane). WATCHPOINTS (SWU). HADC (8 CHAN, 12-BIT). 8. Figure 1. Processor Block Diagram SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog devices , Inc. Rev. B Document Feedback Information furnished by Analog devices is believed to be accurate and reliable.

5 However, no responsibility is assumed by Analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, Box 9106, Norwood, MA 02062-9106 or otherwise under any patent or patent rights of Analog devices . Trademarks and Tel: 2018 Analog devices , Inc. All rights reserved. registered trademarks are the property of their respective owners. Technical Support ADSP-SC582/SC583/SC584/SC587/SC589/ADSP- 21583/21584/21587. TABLE OF CONTENTS. System Features .. 1 GPIO Multiplexing for the 529-Ball CSP_BGA Package.

6 55. Memory .. 1 ADSP-SC58x/ADSP-2158x Designer Quick Reference .. 58. Additional Features .. 1 Specifications .. 79. Table of Contents .. 2 Operating Conditions .. 79. Revision History .. 2 Electrical Characteristics .. 83. General Description .. 3 HADC .. 87. ARM Cortex-A5 Processor .. 5 TMU .. 87. SHARC Processor .. 6 Absolute Maximum Ratings .. 88. SHARC+ core Architecture .. 8 ESD Caution .. 88. System Infrastructure .. 10 Timing Specifications .. 89. System Memory Map .. 11 Output Drive Currents .. 153. Security Features .. 14 Test Conditions .. 155. Security Features Disclaimer .. 15 Environmental Conditions .. 157. Safety Features .. 15 ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Processor Peripherals.

7 15 Assignments .. 158. System Acceleration .. 20 Numerical by Ball Number .. 158. System Design .. 21 Alphabetical by Pin Name .. 160. System Debug .. 23 Configuration of the 349-Ball CSP_BGA .. 162. Development Tools .. 24 ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments .. 163. Additional Information .. 25. Numerical by Ball Number .. 163. Related signal Chains .. 25. Alphabetical by Pin Name .. 166. ADSP-SC58x/ADSP-2158x Detailed signal Descriptions .. 26 Configuration of the 529-Ball CSP_BGA .. 169. 349-Ball CSP_BGA signal Descriptions .. 31 Outline Dimensions .. 170. GPIO Multiplexing for the 349-Ball CSP_BGA Package .. 40 Surface-Mount Design .. 171. 529-Ball CSP_BGA signal Descriptions.

8 43 Automotive Products .. 172. Ordering Guide .. 173. REVISION HISTORY. 12/2018 Rev. A to Rev. B Changes to ADSP-SC58x/ADSP-2158x Designer Quick Refer- Changes to Additional Features .. 1 ence .. 58. Changes to Table 3, General Description .. 3 Deleted Package Information from Specifications .. 79. Changes to One Time Programmable Memory (OTP) .. 10 Changes to Operating Conditions .. 79. Changes to Table 7 and Table 8, System Memory Map .. 11 Changes to Table 28, Operating Conditions .. 79. Changes to Housekeeping Analog -to- digital Converter Changes to Table 29, Clock Related Operating Conditions 81. (HADC) .. 19 Changes to Total Internal Power Dissipation .. 85. Changes to Media Local Bus (Media LB).

9 19 Changes Universal Serial Bus (USB) .. 138. Changes to ADSP-SC58x/ADSP-2158x Detailed signal Descrip- Changes 10/100 EMAC Timing (ETH0 and ETH1) .. 139. tions .. 26 Changes to Program Trace Macrocell (PTM) Timing .. 151. Changes to ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Sig- Changes to Test Conditions .. 155. nal Descriptions .. 31. Changes to Automotive Products .. 172. Changes to ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Sig- nal Descriptions .. 43. Rev. B | Page 2 of 173 | December 2018. ADSP-SC582/SC583/SC584/SC587/SC589/ADSP- 21583/21584/21587. GENERAL DESCRIPTION. The ADSP-SC58x/ADSP-2158x processors are members of the Table 1. Common Product Features SHARC family of products.

10 The ADSP-SC58x processor is based on the SHARC+ dual core and the Arm cortex -A5 Product Features ADSP-SC58x/ADSP-2158x core . The ADSP-SC58x/ADSP-2158x SHARC processors are DAI (includes SRU) 2. members of the SIMD SHARC family of digital signal proces- Full SPORTs 4 per DAI. sors (DSPs) that feature Analog devices , Inc., Super Harvard S/PDIF receive/transmit 1per DAI. Architecture . These 32-bit/40-bit/64-bit floating-point proces- ASRCs 4 pair per DAI. sors are optimized for high performance audio/floating-point applications with large, on-chip, static random-access memory PCGs 2 per DAI. (SRAM), multiple internal buses that eliminate input/output I2C (TWI) 3. (I/O) bottlenecks, and innovative digital audio interfaces (DAI).