Transcription of Single Schmitt trigger buffer - Nexperia
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Single Schmitt trigger buffer - Nexperia
74 LVC1G17. Single Schmitt trigger buffer Rev. 12 8 June 2018 Product data sheet 1 General description The 74 LVC1G17 provides a buffer function with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined outputs. The input can be driven from either V or 5 V devices. This feature allows the use of this device in a mixed V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF. circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2 Features and benefits Wide supply voltage range from V to V. High noise immunity Complies with JEDEC standard JESD8-7 ( V to V). JESD8-5 ( V to V). JESD8B/JESD36 ( V to V). ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V. MM: JESD22-A115-A exceeds 200 V. 24 mA output drive (VCC = V). CMOS low power consumption Latch-up performance exceeds 250 mA. Direct interface with TTL levels Unlimited rise and fall times Inputs accept voltages up to 5 V.
Single Schmitt trigger buffer Rev. 14 — 14 January 2022 Product data sheet 1. General description The 74LVC1G17 is a single buffer Schmitt-trigger. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
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