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Single Schmitt trigger buffer - Nexperia

74 LVC1G17. Single Schmitt trigger buffer Rev. 12 8 June 2018 Product data sheet 1 General description The 74 LVC1G17 provides a buffer function with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined outputs. The input can be driven from either V or 5 V devices. This feature allows the use of this device in a mixed V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF. circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2 Features and benefits Wide supply voltage range from V to V. High noise immunity Complies with JEDEC standard JESD8-7 ( V to V). JESD8-5 ( V to V). JESD8B/JESD36 ( V to V). ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V. MM: JESD22-A115-A exceeds 200 V. 24 mA output drive (VCC = V). CMOS low power consumption Latch-up performance exceeds 250 mA. Direct interface with TTL levels Unlimited rise and fall times Inputs accept voltages up to 5 V.

Single Schmitt trigger buffer Rev. 14 — 14 January 2022 Product data sheet 1. General description The 74LVC1G17 is a single buffer Schmitt-trigger. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

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  Single, Triggers, Buffer, Schmitt, Single schmitt trigger buffer, Single buffer schmitt

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Transcription of Single Schmitt trigger buffer - Nexperia

1 74 LVC1G17. Single Schmitt trigger buffer Rev. 12 8 June 2018 Product data sheet 1 General description The 74 LVC1G17 provides a buffer function with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined outputs. The input can be driven from either V or 5 V devices. This feature allows the use of this device in a mixed V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF. circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2 Features and benefits Wide supply voltage range from V to V. High noise immunity Complies with JEDEC standard JESD8-7 ( V to V). JESD8-5 ( V to V). JESD8B/JESD36 ( V to V). ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V. MM: JESD22-A115-A exceeds 200 V. 24 mA output drive (VCC = V). CMOS low power consumption Latch-up performance exceeds 250 mA. Direct interface with TTL levels Unlimited rise and fall times Inputs accept voltages up to 5 V.

2 Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C. 3 Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74 LVC1G17GW -40 C to +125 C TSSOP5 plastic thin shrink small outline package; SOT353-1. 5 leads; body width mm 74 LVC1G17GV -40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753. Nexperia 74 LVC1G17. Single Schmitt trigger buffer Type number Package Temperature range Name Description Version 74 LVC1G17GM -40 C to +125 C XSON6 plastic extremely thin small outline package; SOT886. no leads; 6 terminals; body 1 x x mm 74 LVC1G17GF -40 C to +125 C XSON6 plastic extremely thin small outline package; SOT891. no leads; 6 terminals; body 1 x 1 x mm 74 LVC1G17GN -40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1115. 6 terminals; body x x mm 74 LVC1G17GS -40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1202. 6 terminals; body x x mm 74 LVC1G17GX -40 C to +125 C X2 SON5 plastic thermal enhanced extremely thin SOT1226.

3 Small outline package; no leads; 5 terminals;. body x x mm 74 LVC1G17GX4 -40 C to +125 C X2 SON4 plastic thermal enhanced extremely thin SOT1269-2. small outline package; no leads; 4 terminals;. body x x mm 4 Marking Table 2. Marking codes [1]. Type number Marking 74 LVC1G17GW VJ. 74 LVC1G17GV V17. 74 LVC1G17GM VJ. 74 LVC1G17GF VJ. 74 LVC1G17GN VJ. 74 LVC1G17GS VJ. 74 LVC1G17GX VJ. 74 LVC1G17GX4 VJ. [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5 Functional diagram A Y. mnb150 mnb151. Figure 1. Logic symbol Figure 2. IEC logic symbol A Y. mnb152. Figure 3. Logic diagram 74 LVC1G17 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reserved. Product data sheet Rev. 12 8 June 2018. 2 / 22. Nexperia 74 LVC1G17. Single Schmitt trigger buffer 6 Pinning information Pinning 74 LVC1G17. 74 LVC1G17. 1 6 VCC. 1 5 VCC. A 2 5 A 2. GND 3 4 Y. 001aaf402. GND 3 4 Y. Transparent top view 001aaf190.

4 Figure 5. Pin configuration SOT886, SOT891, SOT1115. Figure 4. Pin configuration SOT353-1 and SOT753 and SOT1202 (XSON6). 74 LVC1G17 74 LVC1G17. 1 5 VCC A 1 4 VCC. 3. GND. A 2 4 Y GND 2 3 Y. aaa-003025 aaa-028399. Transparent top view Transparent top view Figure 6. Pin configuration SOT1226 (X2 SON5) Figure 7. Pin configuration SOT1269-2 (X2 SON4). Pin description Table 3. Pin description Symbol Pin Description TSSOP5, SC-74A and X2 SON5 XSON6 X2 SON4. 1 1, 5 - not connected A 2 2 1 data input GND 3 3 2 ground (0 V). Y 4 4 3 data output VCC 5 6 4 supply voltage 74 LVC1G17 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reserved. Product data sheet Rev. 12 8 June 2018. 3 / 22. Nexperia 74 LVC1G17. Single Schmitt trigger buffer 7 Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level Input Output A Y. L L. H H. 8 Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).

5 Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage + V. IIK input clamping current VI < 0 V -50 - mA. [1]. VI input voltage + V. IOK output clamping current VO > VCC or VO < 0 V - 50 mA. [1]. VO output voltage Active mode VCC + V. [1]. Power-down mode; VCC = 0 V + V. IO output current VO = 0 V to VCC - 50 mA. ICC supply current - 100 mA. IGND ground current -100 - mA. Tstg storage temperature -65 +150 C. Ptot total power dissipation Tamb = -40 C to +125 C. [2]. TSSOP5, SC-74A, XSON6 and - 250 mW. X2 SON5 package [3]. X2 SON4 package - 150 mW. [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP5 and SC-74A packages: above C the value of Ptot derates linearly with mW/K. For XSON6 and X2 SON5 package: above 118 C the value of Ptot derates linearly with mW/K. [3] For X2 SON4 packages: above 57 C the value of Ptot derates linearly with mW/K.

6 74 LVC1G17 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reserved. Product data sheet Rev. 12 8 June 2018. 4 / 22. Nexperia 74 LVC1G17. Single Schmitt trigger buffer 9 Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage - V. VI input voltage 0 - V. VO output voltage Active mode 0 - VCC V. Power-down mode; VCC = 0 V 0 - V. Tamb ambient temperature -40 - +125 C. 10 Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). [1]. Symbol Parameter Conditions Min Typ Max Unit Tamb = -40 C to +85 C. VOH HIGH-level output voltage VI = VT+ or VT- IO = -100 A; VCC = V to V VCC - - - V. IO = -4 mA; VCC = V - - V. IO = -8 mA; VCC = V - - V. IO = -12 mA; VCC = V - - V. IO = -24 mA; VCC = V - - V. IO = -32 mA; VCC = V - - V. VOL LOW-level output voltage VI = VT+ or VT- IO = 100 A; VCC = V to V - - V.

7 IO = 4 mA; VCC = V - - V. IO = 8 mA; VCC = V - - V. IO = 12 mA; VCC = V - - V. IO = 24 mA; VCC = V - - V. IO = 32 mA; VCC = V - - V. II input leakage current VI = V or GND; VCC = 0 V to V - 1 A. IOFF power-off leakage current VI or VO = V; VCC = 0 V - 2 A. ICC supply current VI = V or GND; - 4 A. VCC = V to V; IO = 0 A. ICC additional supply current per pin; VI = VCC - V; IO = 0 A; - 5 500 A. VCC = V to V. CI input capacitance - 5 - pF. 74 LVC1G17 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reserved. Product data sheet Rev. 12 8 June 2018. 5 / 22. Nexperia 74 LVC1G17. Single Schmitt trigger buffer [1]. Symbol Parameter Conditions Min Typ Max Unit Tamb = -40 C to +125 C. VOH HIGH-level output voltage VI = VT+ or VT- IO = -100 A; VCC = V to V VCC - - - V. IO = -4 mA; VCC = V - - V. IO = -8 mA; VCC = V - - V. IO = -12 mA; VCC = V - - V. IO = -24 mA; VCC = V - - V. IO = -32 mA; VCC = V - - V. VOL LOW-level output voltage VI = VT+ or VT- IO = 100 A; VCC = V to V - - V.

8 IO = 4 mA; VCC = V - - V. IO = 8 mA; VCC = V - - V. IO = 12 mA; VCC = V - - V. IO = 24 mA; VCC = V - - V. IO = 32 mA; VCC = V - - V. II input leakage current VI = V or GND; VCC = 0 V to V - - 1 A. IOFF power-off leakage current VI or VO = V; VCC = 0 V - - 2 A. ICC supply current VI = V or GND; - - 4 A. VCC = V to V; IO = 0 A. ICC additional supply current per pin; VI = VCC - V; IO = 0 A; - - 500 A. VCC = V to V. [1] All typical values are measured at maximum VCC and Tamb = 25 C. 74 LVC1G17 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reserved. Product data sheet Rev. 12 8 June 2018. 6 / 22. Nexperia 74 LVC1G17. Single Schmitt trigger buffer Table 8. Transfer characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 C to +85 C -40 C to +125 C Unit [1]. Min Typ Max Min Max VT+ positive-going see Figure 8 and Figure 9. threshold voltage VCC = V V.

9 VCC = V V. VCC = V V. VCC = V V. VCC = V V. VT- negative-going see Figure 8 and Figure 9. threshold voltage VCC = V V. VCC = V V. VCC = V V. VCC = V V. VCC = V V. VH hysteresis see Figure 8, Figure 9 and voltage Figure 10. VCC = V V. VCC = V V. VCC = V V. VCC = V V. VCC = V V. [1] All typical values are measured at Tamb = 25 C. Transfer characteristic waveforms VO. VT+. VI VH. VT- VO. VI. VH. VT- VT+ mnb154 mnb155. Figure 8. Transfer characteristic Figure 9. Definitions of VT+, VT- and VH. 74 LVC1G17 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reserved. Product data sheet Rev. 12 8 June 2018. 7 / 22. Nexperia 74 LVC1G17. Single Schmitt trigger buffer mna641. 10. ICC. (mA). 8. 6. 4. 2. 0. 0 1 2 VI (V) 3. VCC = V. Figure 10. Typical transfer characteristics 11 Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 12. Symbol Parameter Conditions -40 C to +85 C -40 C to +125 C Unit [1].

10 Min Typ Max Min Max [2]. tpd propagation delay A to Y; see Figure 11. VCC = V to V ns VCC = V to V ns VCC = V ns VCC = V to V ns VCC = V to V ns [3]. CPD power dissipation VI = GND to VCC; - - - - pF. capacitance VCC = V. [1] Typical values are measured at Tamb = 25 C and VCC = V, V, V, V and V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). 2 2. PD = CPD x VCC x fi x N + (CL x VCC x fo) where: fi = input frequency in MHz;. fo = output frequency in MHz;. CL = output load capacitance in pF;. VCC = supply voltage in V;. N = number of inputs switching;. 2. (CL x VCC x fo) = sum of outputs. 74 LVC1G17 All information provided in this document is subject to legal disclaimers. Nexperia 2018. All rights reserved. Product data sheet Rev. 12 8 June 2018. 8 / 22. Nexperia 74 LVC1G17. Single Schmitt trigger buffer Waveform and test circuit VI. A input VM. GND. t PHL t PLH. VOH. Y output VM. VOL mnb153. Measurement points are given in Table 10.