Transcription of Stand-alone CAN controller - NXP
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Stand-alone CAN controller - NXP
DATA SHEETP roduct specificationSupersedes data of 1999 Aug 17 File under Integrated Circuits, IC182000 Jan 04 INTEGRATED CIRCUITSSJA1000 Stand-alone CAN controller2000 Jan 042 Philips SemiconductorsProduct specificationStand-alone CAN controllerSJA1000 CONTENTS1 FEATURES2 GENERAL DESCRIPTION3 ORDERING INFORMATION4 BLOCK DIAGRAM5 PINNING6 FUNCTIONAL of the CAN controller Management Logic (IML) Buffer (TXB) Buffer (RXB, RXFIFO) Filter (ACF) Stream Processor (BSP) Timing Logic (BTL) Management Logic (EML) description of the CAN between BasicCAN and address Register (CR) Register (CMR) Register (SR) Register (IR) buffer address Register (MOD) Register (CMR) Register (SR) Register (IR) Enable Register (IER) Lost Capture register (ALC) Code Capture register (ECC) Warning Limit Register (EWLR) Error Counter Register (RXERR) Error Counter Register (TXERR) Message Counter (RMC) Buffer Start Address register (RBSA) Timi
1 = selects Intel mode 0 = selects Motorola mode VDD3 12 5 V supply for output driver TX0 13 output from the CAN output driver 0 to the physical bus line TX1 14 output from the CAN output driver 1 to the physical bus line VSS3 15 ground for output driver INT 16 interrupt output, used to interrupt the microcontroller; INT is active LOW if any bit of
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