Stand-alone CAN controller - NXP

1 DATA SHEETP roduct specificationSupersedes data of 1999 Aug 17 File under Integrated Circuits, IC182000 Jan 04 INTEGRATED CIRCUITSSJA1000 Stand-alone CAN controller2000 Jan 042 Philips SemiconductorsProduct specificationStand-alone CAN controllerSJA1000 CONTENTS1 FEATURES2 GENERAL DESCRIPTION3 ORDERING INFORMATION4 BLOCK DIAGRAM5 PINNING6 FUNCTIONAL of the CAN controller Management Logic (IML) Buffer (TXB) Buffer (RXB, RXFIFO) Filter (ACF) Stream Processor (BSP) Timing Logic (BTL) Management Logic (EML) description of the CAN between BasicCAN and address Register (CR) Register (CMR) Register (SR) Register (IR) buffer address Register (MOD) Register (CMR) Register (SR) Register (IR) Enable Register (IER) Lost Capture register (ALC) Code Capture register (ECC) Warning Limit Register (EWLR) Error Counter Register (RXERR) Error Counter Register (TXERR) Message Counter (RMC) Buffer Start Address register (RBSA) Timing Register 0 (BTR0) Timing Register 1 (BTR1) Control Register (OCR) Divider Register (CDR)

2 7 LIMITING VALUES8 THERMAL CHARACTERISTICS9DC CHARACTERISTICS10AC timing AC information11 PACKAGE by dipping or by soldered soldered joints13 DEFINITIONS14 LIFE SUPPORT APPLICATIONS2000 Jan 043 Philips SemiconductorsProduct specificationStand-alone CAN controllerSJA10001 FEATURES Pin compatibility to the PCA82C200 Stand-alone CANcontroller Electrical compatibility to the PCA82C200 stand-aloneCAN controller PCA82C200 mode (BasicCAN mode is default) Extended receive buffer (64-byte FIFO) CAN protocol compatibility (extended framepassive in PCA82C200 compatibility mode) Supports 11-bit identifier as well as 29-bit identifier Bit rates up to 1 Mbits/s PeliCAN mode extensions.

3 Error counters with read/write access Programmable error warning limit Last error code register Error interrupt for each CAN-bus error Arbitration lost interrupt with detailed bit position Single-shot transmission (no re-transmission) Listen only mode (no acknowledge, no active errorflags) Hot plugging support (software driven bit ratedetection) Acceptance filter extension (4-byte code, 4-bytemask) Reception of own messages (self reception request) 24 MHz clock frequency Interfaces to a variety of microprocessors Programmable CAN output driver configuration Extended ambient temperature range ( 40 to +125 C).2 GENERAL DESCRIPTIONThe SJA1000 is a Stand-alone controller for the ControllerArea Network (CAN) used within automotive and generalindustrial environments.

4 It is the successor of thePCA82C200 CAN controller (BasicCAN) from PhilipsSemiconductors. Additionally, a new mode of operation isimplemented (PeliCAN) which supports the CAN specification with several new INFORMATIONTYPE NUMBERPACKAGENAMEDESCRIPTIONVERSIONSJA10 00 DIP28plastic dual in-line package; 28 leads (600 mil)SOT117-1 SJA1000 TSO28plastic small outline package; 28 leads; body width mmSOT136-12000 Jan 044 Philips SemiconductorsProduct specificationStand-alone CAN controllerSJA10004 BLOCK Block , full pagewidthMGK623 INTERFACE MANAGEMENT LOGIC78address/datacontrolMESSAGE BUFFERTRANSMITBUFFERRECEIVEBUFFERRECEIVE FIFOBITSTREAMPROCESSORACCEPTANCEFILTERBI T TIMINGLOGICERRORMANAGEMENTLOGICRESETOSCI LLATORXTAL19 XTAL210TX0TX1RX0RX1171821201914131512822 internal busVDD3 VSS3 VDD1 VSS1 VSS2 VDD2AD7 to AD02, 1,28 to 233 to 7,11, 16 ALE/AS, CS,RD/E, WR,CLKOUT,MODE, INT RSTSJA10002000 Jan 045 Philips SemiconductorsProduct specificationStand-alone CAN controllerSJA10005 PINNINGNote1.

5 XTAL1 and XTAL2 pins should be connected to VSS1 via 15 pF to AD02, 1, 28 to 23multiplexed address/data busALE/AS3 ALE input signal ( intel mode), AS input signal (Motorola mode)CS4chip select input, LOW level allows access to the SJA1000RD/E5RD signal ( intel mode) or E enable signal (Motorola mode) from the microcontrollerWR6WR signal ( intel mode) or RD/WR signal (Motorola mode) from the microcontrollerCLKOUT7clock output signal produced by the SJA1000 for the microcontroller; the clocksignal is derived from the built-in oscillator via the programmable divider; the clockoff bit within the clock divider register allows this pin to disableVSS18ground for logic circuitsXTAL19input to the oscillator amplifier; external oscillator signal is input via this pin; note 1 XTAL210output from the oscillator amplifier; the output must be left open-circuit when anexternal oscillator signal is used.

6 Note 1 MODE11mode select input1 = selects intel mode0 = selects Motorola modeVDD3125 V supply for output driverTX013output from the CAN output driver 0 to the physical bus lineTX114output from the CAN output driver 1 to the physical bus lineVSS315ground for output driverINT16interrupt output, used to interrupt the microcontroller;INT is active LOW if any bit ofthe internal interrupt register is set;INT is an open-drain output and is designed tobe a wired-OR with otherINT outputs within the system; a LOW level on this pin willreactivate the IC from sleep modeRST17reset input, used to reset the CAN interface (active LOW); automatic power-on resetcan be obtained by connectingRST via a capacitor to VSS and a resistor to VDD( C = 1 F; R = 50 k )VDD2185 V supply for input comparatorRX0, RX119, 20input from the physical CAN-bus line to the input comparator of the SJA1000;a dominant level will wake up the SJA1000 if sleeping; a dominant level is read, ifRX1 is higher than RX0 and vice versa for the recessive level; if the CBP bit (seeTable 49) is set in the clock divider register, the CAN input comparator is bypassedto achieve lower internal delays if an external transceiver circuitry is connected tothe SJA1000; in this case only RX0 is active.

7 HIGH is interpreted as recessive leveland LOW is interpreted as dominant levelVSS221ground for input comparatorVDD1225 V supply for logic circuits2000 Jan 046 Philips SemiconductorsProduct specificationStand-alone CAN Pin configuration (DIP28).handbook, halfpageAD6AD7 ALE/ASCLKOUTVSS1 XTAL1 XTAL2 MODEVDD3TX0TX1AD5AD4AD3AD2AD0 VDD1AD1 VSS2RX1RX0 VDD2 RSTINTVSS3123456789101112132827262524232 22120191817161514 SJA1000 MGK616 Pin configuration (SO28).handbook, halfpageAD6AD7 ALE/ASCLKOUTVSS1 XTAL1 XTAL2 MODEVDD3TX0TX1AD5AD4AD3AD2AD0 VDD1AD1 VSS2RX1RX0 VDD2 RSTINTVSS3123456789101112132827262524232 22120191817161514 SJA1000 TMGK617 CSRD/EWR2000 Jan 047 Philips SemiconductorsProduct specificationStand-alone CAN controllerSJA10006 FUNCTIONAL of the CAN controller (IML)The interface management logic interprets commandsfrom the CPU, controls addressing of the CAN registersand provides interrupts and status information to the (TXB)The transmit buffer is an interface between the CPU andthe Bit Stream Processor (BSP) that is able to store acomplete message for transmission over the CANnetwork.

8 The buffer is 13 bytes long, written to by the CPUand read out by the (RXB, RXFIFO)The receive buffer is an interface between the acceptancefilter and the CPU that stores the received and acceptedmessages from the CAN-bus line. The Receive Buffer(RXB) represents a CPU-accessible 13-byte window of theReceive FIFO (RXFIFO), which has a total length of64 the help of this FIFO the CPU is able to process onemessage while other messages are being (ACF)The acceptance filter compares the received identifier withthe acceptance filter register contents and decideswhether this message should be accepted or not. In theevent of a positive acceptance test, the complete messageis stored in the (BSP)The bit stream processor is a sequencer which controls thedata stream between the transmit buffer, RXFIFO and theCAN-bus.

9 It also performs the error detection, arbitration,stuffing and error handling on the (BTL)The bit timing logic monitors the serial CAN-bus line andhandles the bus line-related bit timing. It is synchronized tothe bit stream on the CAN-bus on a recessive-to-dominant bus line transition at the beginningof a message (hard synchronization) and re-synchronizedon further transitions during the reception of a message(soft synchronization). The BTL also providesprogrammable time segments to compensate for thepropagation delay times and phase shifts ( due tooscillator drifts) and to define the sample point and thenumber of samples to be taken within a bit (EML)The EML is responsible for the error confinement of thetransfer-layer modules.

10 It receives error announcementsfrom the BSP and then informs the BSP and IML abouterror description of the CAN controllerThe SJA1000 is designed to be software andpin-compatible to its predecessor, the PCA82C200stand-alone CAN controller . Additionally, a lot of newfunctions are implemented. To achieve the softwarecompatibility, two different modes of operation areimplemented: BasicCAN mode; PCA82C200 compatible PeliCAN mode; extended mode of operation is selected with the CAN-mode bitlocated within the clock divider register. Default modeupon reset is the BasicCAN BasicCAN mode the SJA1000 emulates all knownregisters from the PCA82C200 Stand-alone CANcontroller.