Transcription of Ternary Logic Gates & Arithmetic Circuit - Ijiset
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Ijiset - International Journal of Innovative Science, Engineering & Technology, Vol. 1 Issue 10, December 2014. ISSN 2348 7968 Ternary Logic Gates & Arithmetic Circuit Priyanka Vyawahare1, Anupama Deshmukh2 , Ankita Chandurkar3 1 Department of Electronics & Telecommunication Engineering Prof. Rram Meghe Institute Of Technology and research, Badnera, Amravati Maharashtra 444701,India 2 Department of Electronics & Telecommunication Engineering Prof. Rram Meghe Institute Of Technology and research, Badnera, Amravati Maharashtra 4447001,India 3 Department of Elecronics & Communication Engineering Abha Gaikwad-Patil College of Engineering & Technology ,Nagpur, Maharashtra441108,India Abstract Scaling of conventi
IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 1 Issue 10, December 2014. www.ijiset.com ISSN 2348 – 7968
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