Transcription of TMS320VC5402 Datasheet - TI.com
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TMS320VC5402 Datasheet - TI.com
SPRS079G OCTOBER 1998 REVISED OCTOBER 2008. D Advanced Multibus Architecture With Three D Arithmetic Instructions With Parallel Store Separate 16-Bit Data Memory Buses and and Parallel Load One Program Memory Bus D Conditional Store Instructions D 40-Bit Arithmetic Logic Unit (ALU), D Fast Return From Interrupt Including a 40-Bit Barrel Shifter and Two D On-Chip Peripherals Independent 40-Bit Accumulators Software-Programmable Wait-State D 17- 17-Bit Parallel Multiplier Coupled to a Generator and Programmable Bank 40-Bit Dedicated Adder for Non-Pipelined Switching Single-Cycle Multiply/Accumulate (MAC) On-Chip Phase-Locked Loop (PLL) Clock Operation Generator With Internal Oscillator or D Compare, Select, and Store Unit (CSSU) for External Clock Source the Add/Compare Selection of the Viterbi Two Multichannel Buffered Serial Ports Operator (McBSPs)
SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 1 Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and
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