Tutorial on Digital Phase-Locked Loops - CppSim

Tutorial onDigital Phase-Locked LoopsCICC 2009 Michael H. PerrottSeptember 2009 Copyright 2009 by Michael H. PerrottWhy Are Digital Phase-Locked Loops Interesting? Performance is important-Phase noise can limit wireless transceiver performance-Jitter can be a problem for Digital processors The standard analog PLL implementation is problematic in many applications -Analog building blocks on a mostly Digital chip pose design and verification challenges-The cost of implementation is becoming too high ..Can Digital Phase-Locked Loops offer excellent performance with a lower cost of implementation?Just Enough PLL Background .. PerrottWhat is a Phase-Locked Loop (PLL)?de BellescizeOnde Electr, 1932e(t)v(t)out(t)ref(t) VCO efficiently provides oscillating waveform with variable frequency PLL synchronizes VCO frequency to input reference frequency through feedback-Key block is phase detector Realized as Digital gatesthat create pulsed signalsAnalogLoop FilterPhaseDetectVCOref(t)out(t)e(t)v(t) ref(t)out(t)e(t)v(t) PerrottInteger-N Frequency Synthesizers Use Digital counter structure to divide VCO frequency-Constraint: must divide by integer values Use PLL to synchronize reference and divider outputSepe and JohnstonUS Patent (1968)Output frequency is digitally controllede(t)v(t)out(t)ref(t)AnalogLoop FilterPhaseDetectVCOref(t)div(t)e(t)v(t) DividerNFout = N Frefdiv(t)

M.H. Perrott 2 Why Are Digital Phase-Locked Loops Interesting? Performance is important-Phase noise can limit wireless transceiver performance-Jitter can be a problem for digital processors The standard analog PLL implementation is problematic in many applications-Analog building blocks on a mostly digital chip pose - design and verification challenges

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