Tutorial on Digital Phase-Locked Loops - CppSim

1 Tutorial onDigital Phase-Locked LoopsCICC 2009 Michael H. PerrottSeptember 2009 Copyright 2009 by Michael H. PerrottWhy Are Digital Phase-Locked Loops Interesting? Performance is important-Phase noise can limit wireless transceiver performance-Jitter can be a problem for Digital processors The standard analog PLL implementation is problematic in many applications -Analog building blocks on a mostly Digital chip pose design and verification challenges-The cost of implementation is becoming too high ..Can Digital Phase-Locked Loops offer excellent performance with a lower cost of implementation?Just Enough PLL Background .. PerrottWhat is a Phase-Locked Loop (PLL)?de BellescizeOnde Electr, 1932e(t)v(t)out(t)ref(t) VCO efficiently provides oscillating waveform with variable frequency PLL synchronizes VCO frequency to input reference frequency through feedback-Key block is phase detector Realized as Digital gatesthat create pulsed signalsAnalogLoop FilterPhaseDetectVCOref(t)out(t)e(t)v(t) ref(t)out(t)e(t)v(t) PerrottInteger-N Frequency Synthesizers Use Digital counter structure to divide VCO frequency-Constraint.

2 Must divide by integer values Use PLL to synchronize reference and divider outputSepe and JohnstonUS Patent (1968)Output frequency is digitally controllede(t)v(t)out(t)ref(t)AnalogLoop FilterPhaseDetectVCOref(t)div(t)e(t)v(t) DividerNFout = N Frefdiv(t) PerrottFractional-N Frequency Synthesizers Dither divide value to achieve fractional divide values-PLL loop filter smooths the resulting variationsVery high frequency resolution is achievedWellsUS Patent (1984)RileyUS Patent (1989)JSSC 93 Kingsford-SmithUS Patent (1974)e(t)v(t)out(t)ref(t)AnalogLoop FilterPhaseDetectVCOD ividerN[k]Fout = Frefdiv(t) Nsd[k] (t)div(t)e(t)v(t) PerrottThe Issue of Quantization Noise Limits PLL bandwidth Increases linearity requirements of phase detectore(t)v(t)out(t)ref(t)AnalogLoop FilterPhaseDetectVCOD ividerN[k]Fout = Frefdiv(t) Nsd[k] (t)div(t)e(t)v(t)f Quantization NoiseStriving for a Better PLL PerrottAnalog Phase Detection Pulse width is formed according to phase difference between two signals Average of pulsed waveform is applied to VCO inputout(t)ref(t)AnalogLoop FilterPhaseDetectVCORegDQref(t)div(t)pha se errorDQreset11ref(t)error(t)div(t)error( t)Dividerdiv(t) PerrottTradeoffs of Analog Approach Benefit: average of pulsed output is a continuous, linear function of phase error Issue: analog loop filter implementation is undesirableref(t)div(t)error(t)Phase DetectorCharacteristicPhase Detector Signalsout(t)AnalogLoop FilterPhaseDetectVCOphase errorAverage oferror(t)Dividerref(t)div(t) PerrottIssues with Analog Loop Filter Charge pump: output resistance, mismatch Filter caps: leakage current, large areaout(t)ref(t)AnalogLoop FilterPhaseDetectVCOerror(t) PerrottGoing Digital .

3 Digital loop filter: compact area, insensitive to leakage Challenges: -Time-to- Digital Converter (TDC)-Digitally-Controlled Oscillator (DCO)Staszewski et. al.,TCAS II, Nov 2003out(t)ref(t)AnalogLoop FilterPhaseDetectVCOTime-to-Digitalout(t )ref(t)DigitalLoop PerrottOutline of Talk Overview of Key Blocks (TDC and DCO) Modeling & CAD Tools High Performance TDC design Quantization Noise Cancellation DCO based on an efficient passive DAC structure Divider Design Loop Filter Design Prototype with measured PerrottTime-to-Digitalout(t)ref(t)Digita lLoop FilterDCOdiv(t)RegDQDelayRegDQRegDQDelay Delayref(t)e[k]Dividerdiv(t)ref(t)div(t) e[k]11100 DelayClassical Time-to- Digital Converter Resolution set by a Single Delay Chain structure-Phase error is measured with delays and registers Corresponds to a flash PerrottTime-to-Digitalout(t)ref(t)Digita lLoop FilterDCOD ividerdiv(t)ref(t)div(t)e[k]11100 Phase DetectorCharacteristicphase errordetectoroutputDelay varies due to mismatchImpact of Limited Resolution and Delay Mismatch Integer-N PLL-Limit cycles due to limited resolution (unless high ref noise) Fractional-N PLL-Fractional spurs due to non-linearity from delay PerrottModeling of TDC Phase error converted to time error by scale factor: T/2 TDC introduces quantization error: tq[k] TDC gain set by average delay per step.

4 TdelTime-to-Digitalout(t)ref(t)DigitalLo op FilterDCOquantizationerrorphaseerror[k]e [k]Phase DetectorCharacteristictime errordetectoroutputT2 tq[k]Dividerdiv(t)referenceperiodTTDCGai n1 tdel PerrottTime-to-Digitalout(t)ref(t)Digita lLoop FilterDCOD ividerdiv(t)VaractorVaractorAnalogContro lDACA Straightforward Approach for Achieving a DCO Use a DAC to control a conventional LC oscillator-Allows the use of an existing VCO within a Digital PLL-Can be applied across a broad range of IC processesFerriss ISSCC 2007 Hsu ISSCC PerrottA Much More Digital Implementation Adjust frequency in an LC oscillator by switching in a variable number of small capacitors-Most effective for CMOS processes of and belowStaszewski et. al.,TCAS II, Nov 2003 Time-to-Digitalout(t)ref(t)DigitalLoop FilterDCOD ividerdiv(t) PerrottLeveraging Segmentation in Switched Capacitor DCO Similar in design as segmentedcapacitor DAC structures-Binary array: efficient control, but may lack monotonicity-Unit element array: monotonic, but complex control Coarse and fine control segmentation of DCO-Coarse control: active only during initial frequency tuning (leverage binary array)-Fine control.

5 Controlled by PLL feedback (leverage unit element array to guarantee monotonicity)VaractorVaractor1x2x4x2nx1x 1x1x1xBinary ArrayUnit Element PerrottLeveraging Dithering for Fine Control of DCO Increase resolution by dithering of fine cap array Reduce noise from dithering by-Using small unit caps in the fine cap array-Increasing the dithering frequency (defined as 1/Tc) We will assume 1/Tc= M/T( M times reference frequency)VaractorVaractorCoarseControlF ineControlInitialFrequencyTuningTDivide- by-KTc=T/MDigital Modulatorin[k]DigitalLoopFilterref(t)out (t)TDC PerrottHntf(z)z=ej2 fTcTcM2 Kvss=j2 fin[k]qraw[k] out(t)q[k]PhaseNoiseffQuantizationNoise Phase noise-Same as for conventional VCO (tank Q, etc.) Quantization noise from dithering-See Section 3 of Supplemental SlidesCalculation of Noise Spectrum: Switched Cap PerrottfStq(ej2 fT)TDC-referredNoisee[k]T2 tq[k]TDCGain1 tdel ref[k]H(z)LoopFilter2 Kvs n(t)1TT1 NDT-CTCT-DT div[k] out(t)TDCDCOD ividerS n(f)-20 dB/decfDCO-referredNoisez=ej2 fTs=j2 fOverall Digital PLL Model TDC and DCO-referred noise influence overall phase noise according to associated transfer functions to output Calculations involve both discrete andcontinuous PerrottKey Transfer Functions TDC-referred noise DCO-referred noisee[k]T2 tq[k]TDCGain1 tdel ref[k]H(z)LoopFilter2 Kvs n(t)1TT1 NDT-CTCT-DT div[k] out(t)z=ej2 fTs=j2 Perrott Define open loop transfer function A(f)as: Define closed loop parameterizing function G(f)as:-Note.

6 G(f)is a lowpass filter with DC gain = 1 Introduce a Parameterizing Functione[k]T2 tq[k]TDCGain1 tdel ref[k]H(z)LoopFilter2 Kvs n(t)1TT1 NDT-CTCT-DT div[k] out(t)z=ej2 fTs=j2 PerrottTransfer Function Parameterization Calculations TDC-referred noise DCO-referred Perrotte[k]T2 tq[k]TDCGain1 tdel ref[k]H(z)LoopFilter2 Kvs n(t)1TT1 NDT-CTCT-DT div[k] out(t)z=ej2 fTs=j2 fKey Observations TDC-referred noiseLowpass with a DCgain of 2 NHighpass with a highfrequency gain of 1 DCO-referred noiseHow do we calculate the output phase noise? PerrottSpectral Density Calculations CT CT DT DT DT CTCT CTx[k]H(f)y(t)x[k]H(ej2 fT)y[k]x(t)H(f)y(t)DT DTDT Perrottfofo2 N G(f)1-G(f)S n(f)-20 dB/decfDCO-referredNoisefTDC-referredNoi setq[k] n(t) out(t)Stq(ej2 fT)fdBc/HzfoG(f)2 NT12 Stq(ej2 fT)S n(f)G(f)1-2 Phase Noise Calculation TDC noise-DT to CT calculation-Dominates PLL phase noise at low frequency offsets DCO noise-CT to CT calculation-Dominates PLL phase noise at high frequency PerrottExample Calculation for Delay Chain TDC Note.

7 G(f) = 1 at low offset frequencies Ref freq = 1/T= 50 MHz, Out freq = GHz Inverter delay = tdel= 20 psfofo2 N G(f)ftq[k]fG(f)2 NT12 tdel122 tdel122 Stq(ej2 fT)S out(f)tdcCAD PerrottClosed Loop PLL Design Approach Classical open loop approach-Indirectly design G(f)using bode plots of A(f) Proposed closed loop approach-Directly design G(f)by examining impact of its specifications on phase noise (and settling time)-Solve for A(f)that will achieve desired G(f)Implemented in PLL Design AssistantSoftwareLau and Perrott, DAC, June 2003 Closed-LoopPerformanceSpecificationsG(f) A(f)1+A(f)=A(f)G(f)1-G(f)=|A(f)|A(f){K,f p,fz, ..}Open-LoopCharacteristicsClosed-LoopTr ansferFunctionG(f)Open-LoopDesignApproac h{fo, type, order}Proposed Closed Loop Design PerrottEvaluate Phase Noise with 500 kHz PLL Bandwidth Key PLL parameters:-G(f): 500 kHz BW, Type II, 2ndorder rolloff-TDC noise: dBc/Hz-DCO noise: -153 dBc/Hz at 20 MHz offset ( GHz carrier) Perrott103104105106107-160-150-140-130-1 20-110-100-90-80-70-60 Output Phase Noise of SynthesizerFrequency Offset (Hz)L(f) (dBc/Hz)Detector NoiseVCO Noise Total Noise GSM Mask(Referenced to GHz carrier)DCO NoiseTDC NoiseOverall PLLP hase NoiseCalculated Phase Noise Spectrum with 500 kHz BWTDC noise too high for GSM mask with 500 kHz PLL PerrottChange PLL Bandwidth to 100 kHz Key PLL parameters:-G(f): 100 kHz BW, Type= 2, 2ndorder rolloff-TDC noise: dBc/Hz-DCO noise.

8 -153 dBc/Hz at 20 MHz offset ( GHz carrier) Perrott103104105106107-160-150-140-130-1 20-110-100-90-80-70-60 Output Phase Noise of SynthesizerFrequency Offset (Hz)L(f) (dBc/Hz)Detector NoiseVCO Noise Total Noise GSM Mask(Referenced to GHz carrier)DCO NoiseTDC NoiseOverall PLLP hase NoiseCalculated Phase Noise Spectrum with 100 kHz BWGSM mask is met with 100 kHz PLL PerrottLoop Filter Design using PLL Design Assistant PLL Design Assistant allows fast loop filter design-See Section 4 of Supplemental Slides Assumption: Type = 2, 2ndorder rolloff-Where: PLL Design Assistant provides the values of K, wp= 2 fp, wz= 2 PerrottExample Digital Loop Filter Calculation Assumptions-Ref freq (1/T) = 50 MHz, Out freq = GHz (so N= 72)- tdel= 20 ps, Kv= 12 kHz/unit cap-100 kHz bandwidth, Type= 2 , 2ndorder PerrottVerify Calculations Using C++ Behavioral Modeling Schematic-Hierarchical description of system topology Code blocks-Specification of modulebehaviorusing templatedC++ code Behavioral environment allows efficient architectural investigation and validation of calculations-Fast simulation speed is essential for design investigationPFDC hargePump ModulatorLoopFilterDividerCppSim ModuleDescriptionNameInputs, OutputsParametersCodeCppSim ModuleDescriptionNameInputs, PerrottCppSim A Fast C++ Behavioral Do We Improve TDC Performance?

9 Two Key Issues: TDC resolution Perrottfofo2 N G(f)1-G(f)S n(f)-20 dB/decfDCO-referredNoisefTDC-referredNoi setq[k] n(t) out(t)fdBc/HzStq(ej2 fT)fdBc/HzfofoLow PLL BandwidthHigh PLL BandwidthDCON oiseTDCN oiseTDCN oiseDCON oise PLL bandwidth dramatically influences relative impact of TDC and VCO noiseWant high PLL bandwidth?MotivationNeed lowTDC Perrottdiv(t)RegDQDelayRegDQRegDQDelayDe layref(t)e[k]ref(t)div(t)e[k]11100 Delaydiv(t)RegDQDelayRegDQRegDQDelayDela yref(t)e[k]Delay2 Delay2 Delay2div(t)Delayref(t)Delay2e[k]11100 VernierImprove Resolution with Vernier Delay TechniqueEffective Perrottdiv(t)RegDQDelayRegDQRegDQDelayDe layref(t)e[k]Delay2 Delay2 Delay2div(t)Delayref(t)Delay2e[k]11100 VernierIssues with Vernier Approach Mismatch issues are more severe than the single delay chain TDC-Reduced delay is formed as differenceof two delays Large measurement range requires large area-Initial PLL frequency acquisition may require a large rangeEffective PerrottVernierdiv(t)ref(t)Coarsee[k]Dela yDelayDelayDelay2 Delay2 Delay2 DelayDelayDelayRegDQRegDQRegDQRegDQRegDQ RegDQLogicMuxFinee[k]Single Delay ChainDelayDelay - Delay2 Two-Step TDC Architecture Allows Area Reduction Single delay chain provides coarse resolution (Folded)

10 Vernier provides fine resolutionRamakrishnan, BalsaraVLSID PerrottSingle Delay Chaindiv(t)ref(t)Coarsee[k]DelayDelayDel ayDelayDelayDelayRegDQRegDQRegDQRegDQReg DQRegDQLogicMuxFinee[k]Single Delay ChainDelayDelayTimeAmplifierAmplificatio nof Time Single delay chain provides coarse and fine resolution Time amplification is used to improve resolutionSimplified view of: Lee, AbidiVLSI 2007 Two-Step TDC Using Time PerrottLeveraging Metastability to Create a Time Amplifier Metastability leads to progressively slower output transitions as setup time on latch is encroached upon-Time difference at input is amplified at outputSimplified view of: Abas, et al., Electronic Letters, Nov 2002(note that actual implementation uses SR latch)TimeAmplifierLatchDQin(t)ref(t)out (t)ref(t)in(t)out(t)ref(t)in(t)out(t)ref (t) tin tin tout toutin(t)out(t) PerrottInterpolating time-to- Digital converter Interpolate between edges to achieve fine resolution Cyclic approach can also be used for large rangeTstopStartStopTqTin11111 OutStopStartDelayDelayDelayRegistersOut1 0 Henzler et al.