Understanding Verilog Blocking and Nonblocking …

Understanding Verilog BlockingUnderstanding Verilog Blockingand Nonand Non-- Blocking Assignmentsblocking AssignmentsInternational CadenceInternational CadenceUser Group ConferenceUser Group ConferenceSeptember 11, 1996 September 11, 1996presented bypresented byStuart SutherlandStuart SutherlandSutherland HDL ConsultingSutherland HDL ConsultingAbout the PresenterAbout the PresenterStuart Sutherland has over 8 years of experience using Verilog wStuart Sutherland has over 8 years of experience using Verilog with a variety of software tools. He ith a variety of software tools. He holds a BS degree in Computer Science, with an emphasis on Electholds a BS degree in Computer Science, with an emphasis on Electronic Engineering, and has ronic Engineering, and has worked as a design engineer in the defense industry, and as an Aworked as a design engineer in the defense industry, and as an Applications Engineer for Gateway pplications Engineer for Gateway Design Automation (the originator of Verilog ) and Cadence DesignDesign Automation (the originator of Verilog ) and Cadence DesignSystems.

4 Sutherland H D L ObjectivesObjectives The primary objective is to understand: What type of hardware is represented by blocking and non-blocking assignments? The material presented is a subset of an advanced Verilog HDL training course

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  Understanding, Objectives, Understand, Blocking, Verilog, Understanding verilog blocking and

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