Understanding Verilog Blocking and Nonblocking …

1 Understanding Verilog BlockingUnderstanding Verilog Blockingand Nonand Non-- Blocking Assignmentsblocking AssignmentsInternational CadenceInternational CadenceUser Group ConferenceUser Group ConferenceSeptember 11, 1996 September 11, 1996presented bypresented byStuart SutherlandStuart SutherlandSutherland HDL ConsultingSutherland HDL ConsultingAbout the PresenterAbout the PresenterStuart Sutherland has over 8 years of experience using Verilog wStuart Sutherland has over 8 years of experience using Verilog with a variety of software tools. He ith a variety of software tools. He holds a BS degree in Computer Science, with an emphasis on Electholds a BS degree in Computer Science, with an emphasis on Electronic Engineering, and has ronic Engineering, and has worked as a design engineer in the defense industry, and as an Aworked as a design engineer in the defense industry, and as an Applications Engineer for Gateway pplications Engineer for Gateway Design Automation (the originator of Verilog ) and Cadence DesignDesign Automation (the originator of Verilog ) and Cadence DesignSystems.

2 Mr. Sutherland has Systems. Mr. Sutherland has been providing Verilog HDL consulting services since 1991. As abeen providing Verilog HDL consulting services since 1991. As aconsultant, he has been actively consultant, he has been actively involved in using the Veriloginvolved in using the Veriloglangiagelangiagewith a many different of software tools for the design ofwith a many different of software tools for the design ofASICsASIC sand systems. He is a member of the IEEE 1364 standards committand systems. He is a member of the IEEE 1364 standards committee and has been involved ee and has been involved in the specification and testing of Verilog simulation products in the specification and testing of Verilog simulation products from several EDA vendors, including from several EDA vendors, including the Intergraphthe Intergraph--VeriBest VeriBest VeriBestVeriBestsimulator, the Mentorsimulator, the MentorQuickHDLQ uickHDLsimulator, and the Frontlinesimulator, and the FrontlineCycleDriveCycleDrivecycle based simulator.

3 In addition to Verilog designcycle based simulator. In addition to Verilog designconsutltingconsutlting, Mr. Sutherland , Mr. Sutherland provides expert onprovides expert on--site Verilog training on the Verilog HDL language andsite Verilog training on the Verilog HDL language andProgramingProgramingLanguage Language Interface. Mr. Sutherland is the author and publisher of the poInterface. Mr. Sutherland is the author and publisher of the popular pular Verilog IEEE 1364 Quick Verilog IEEE 1364 Quick Reference Guide Reference Guide and the and the Verilog IEEE 1364 PLI Quick Reference Guide Verilog IEEE 1364 PLI Quick Reference Guide ..PleasePleaseconactconactMr. Sutherland with any questions about this material!Mr. Sutherland with any questions about this material!

4 Phone: (503) 692phone: (503) 692--08980898fax: (503) 692fax: (503) 692--15121512ee--mail:mail:stuartstuart@ HDL ConsultingSutherland HDL ConsultingVerilog Consulting and Training ServicesVerilog Consulting and Training Services22805 SW 9222805 SW 92ndndPlacePlaceTualatin, OR 97062 USAT ualatin, OR 97062 USAThe material in this presentation is copyrighted by Sutherland HThe material in this presentation is copyrighted by Sutherland HDL Consulting, DL Consulting, Tualatin, Oregon. The presentation is printed with permission aTualatin, Oregon. The presentation is printed with permission as part of the s part of the proceedings of the 1996 International Cadence User Group Confereproceedings of the 1996 International Cadence User Group Conference.

5 All rights nce. All rights are reserved. No material from this presentation may be duplicaare reserved. No material from this presentation may be duplicated or transmitted by ted or transmitted by any means or in any form without the express written permission any means or in any form without the express written permission of Sutherland HDL of Sutherland HDL noticecopyright noticeSutherland HDL ConsultingSutherland HDL Consulting22805 SW 9222805 SW 92ndndPlacePlaceTualatin, OR 97062 USAT ualatin, OR 97062 USAphone: (503) 692phone: (503) 692--08980898fax: (503) 692fax: (503) 692--15121512ee--mail: info@mail: 1996199644 SutherlandSutherlandSutherlandHHHDDDLLLO bjectivesObjectivesObjectives The primary objective is to understand :The primary objective is to understand :What type of hardware is representedWhat type of hardware is representedby Blocking and nonby Blocking and non-- Blocking Blocking assignments?

6 Assignments? The material presented is a subset of an advanced Verilog The material presented is a subset of an advanced Verilog HDL training courseHDL training course55 SutherlandSutherlandSutherlandHHHDDDLLLP rocedural AssignmentsProcedural AssignmentsProcedural Assignments Procedural assignment evaluation can be modeled as:Procedural assignment evaluation can be modeled as: BlockingBlocking NonNon--blockingblocking Procedural assignment execution can be modeled as:Procedural assignment execution can be modeled as: SequentialSequential ConcurrentConcurrent Procedural assignment timing controls can be modeled as:Procedural assignment timing controls can be modeled as: Delayed evaluationsDelayed evaluations Delayed assignmentsDelayed assignments66 SutherlandSutherlandSutherlandHHHDDDLLLB locking Procedural AssignmentsBlocking Blocking Procedural AssignmentsProcedural Assignments The The ==token represents a token represents a blockingblockingprocedural assignmentprocedural assignment Evaluated and assigned in a single stepEvaluated and assigned in a single step Execution flow within the procedure is blocked until the Execution flow within the procedure is blocked until the assignment is completedassignment is completed Evaluations of concurrent statements in the same time step Evaluations of concurrent statements in the same time step are blocked until the assignment is completedare blocked until the assignment is completedThese examples will These examples will

7 Notnotwork work Why not?Why not?//swap bytes in wordalways @(posedge clk)beginword[15:8] = word[ 7:0];word[ 7:0] = word[15:8];end//swap bytes in wordalways @(posedge clk)beginword[15:8]=word[ 7:0];word[ 7:0] =word[15:8];end//swap bytes in wordalways @(posedge clk)forkword[15:8] = word[ 7:0];word[ 7:0] = word[15:8];join//swap bytes in wordalways @(posedge clk)forkword[15:8]=word[ 7:0];word[ 7:0] =word[15:8];join77 SutherlandSutherlandSutherlandHHHDDDLLLN on- Blocking Procedural AssignmentsNonNon-- Blocking Blocking Procedural AssignmentsProcedural Assignments The The <=<=token represents a token represents a nonnon--blockingblockingassignmentassign ment Evaluated and assigned in two steps:Evaluated and assigned in two steps: The rightThe right--hand side is evaluated immediatelyhand side is evaluated immediately The assignment to the leftThe assignment to the left--hand side is postponed until hand side is postponed until other evaluations in the current time step are completedother evaluations in the current time step are completed Execution flow within the procedure continues until a Execution flow within the procedure continues until a timing control is encountered (flow is not blocked) timing control is encountered (flow is not blocked) These examples will work These examples will work Why?

8 Why?//swap bytes in wordalways @(posedge clk)beginword[15:8] <= word[ 7:0];word[ 7:0] <= word[15:8];end//swap bytes in wordalways @(posedge clk)beginword[15:8]<=word[ 7:0];word[ 7:0] <=word[15:8];end//swap bytes in wordalways @(posedge clk)forkword[15:8] <= word[ 7:0];word[ 7:0] <= word[15:8];join//swap bytes in wordalways @(posedge clk)forkword[15:8]<=word[ 7:0];word[ 7:0] <=word[15:8];join88 SutherlandSutherlandSutherlandHHHDDDLLLR epresenting Simulation Time as QueuesRepresenting Representing Simulation Time as QueuesSimulation Time as Queues Each Verilog simulation time step is divided into 4 queuesEach Verilog simulation time step is divided into 4 queuesNote: this is an abstract view, not how simulation algorithms arNote: this is an abstract view, not how simulation algorithms are implementede implementedTime 0: Q1 (in any order) : Evaluate RHS of all non- Blocking assignments Evaluate RHS and change LHS of all Blocking assignments Evaluate RHS and change LHS of all continuous assignments Evaluate inputs and change outputs of all primitives Evaluate and print output from $display and $write Q2 (in any order) : Change LHS of all non- Blocking assignments Q3 (in any order).

9 Evaluate and print output from $monitor and $strobe Call PLI with reason_synchronize Q4 : Call PLI with reason_rosynchronizeTime 1:..Time 0: Q1 (in any order) : Evaluate RHS of all non- Blocking assignments Evaluate RHS and change LHS of all Blocking assignments Evaluate RHS and change LHS of all continuous assignments Evaluate inputs and change outputs of all primitives Evaluate and print output from $display and $write Q2 (in any order) : Change LHS of all non- Blocking assignments Q3 (in any order) : Evaluate and print output from $monitor and $strobe Call PLI with reason_synchronize Q4 : Call PLI with reason_rosynchronizeTime 1:..99 SutherlandSutherlandSutherlandHHHDDDLLLS equentialProcedural AssignmentsSequentialSequentialProcedura l AssignmentsProcedural Assignments The order of evaluation is The order of evaluation is determinatedeterminate A A sequential Blocking assignmentsequential Blocking assignmentevaluates and assigns evaluates and assigns before continuing on in the procedurebefore continuing on in the procedurealways @(always @(posedge clkposedge clk))beginbeginA A ==1;1;#5 B #5 B ==A + 1;A + 1.

10 Endendevaluate and assign A immediatelyevaluate and assign A immediatelydelay 5 time units, then evaluate and assigndelay 5 time units, then evaluate and assign A A sequential nonsequential non-- Blocking assignmentblocking assignmentevaluates, then evaluates, then continues on to the next timing control before assigningcontinues on to the next timing control before assigningalways @(always @(posedge clkposedge clk))beginbeginA A <=<=1;1;#5 B #5 B <=<=A + 1;A + 1;endendevaluate A immediately; assign at end of time stepevaluate A immediately; assign at end of time stepdelay 5 time units, then evaluate; then assign at delay 5 time units, then evaluate; then assign at end of time step (clock + 5)end of time step (clock + 5)1010 SutherlandSutherlandSutherlandHHHDDDLLLC oncurrentProcedural AssignmentsConcurrentConcurrentProcedura l AssignmentsProcedural AssignmentsThe order of concurrent evaluation is The order of concurrent evaluation is indeterminateindeterminate Concurrent Concurrent Blocking assignmentsblocking assignmentshave have unpredictable resultsunpredictable resultsalways @(always @(posedge clkposedge clk))#5 A #5 A ==A + 1;A + 1;always @(always @(posedge clkposedge clk))#5 B #5 B ==A + 1;A + 1.