Transcription of The proposed SystemVerilog-2012 Standard - …
1 Keeping Up with Chip the proposed systemverilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More EfficientStuart SutherlandSystemVerilog Trainer and ConsultantSutherland HDL, , FitzpatrickVerification EvangelistMentor Graphics, , Abstract The complexity and size of our hardware designsand verification code continues to increase at a rapid rate,and the systemverilog Design and Verification language iskeeping pace. As soon as the systemverilog standardsorganization completed the systemverilog -2009 Standard ,they immediately began work on the next generation of thelanguage, looking for ways to more efficiently and moreeffectively model and verify increasingly complex designs.
2 Injust three years near record time for a complex IEEE Standard a systemverilog - 2012 Standard has been definedand is currently in the balloting process. New and powerfullanguage features include multiple class inheritance, user-defined net types, additional assertion capabilities, and muchmore. You won't need to wait long to use systemverilog - 2012 ;EDA companies have already begun adding systemverilog - 2012 features to their software tools. This paper presents the many new features in the proposedSystemVerilog Standard , and discusses how key new languagecapabilities can enable more efficiently verifying designs thatare continually increasing in size and complexity.
3 The paperalso discusses how new features such as multiple inheritancecan benefit the UVM verification methodology. SystemVerilogis keeping up with Chip your Verilog, systemverilog , hardware design,hardware verification, UVMI. INTRODUCTIONS ystemVerilog has become a primary language for thedesign and verification of digital hardware was first introduced in 2002 as an Accellerastandard that specified a large number of extensions to theVerilog-2001 Hardware Description Language[1]. Theseextensions added both new modeling and verificationcapabilities to Verilog. In 2005, the IEEE standardizedthese extensions as the 1800-2005 SystemVerilogstandard[2].
4 A brief description of these extensions can befound in [3] and [4]. The base Verilog language remained aseparate Standard , IEEE 1364-2005. The 1800-2005 systemverilog Standard only specified enhancements tothe base Verilog 2009, the IEEE approved the 1800-2009 systemverilog Standard [5]. systemverilog -2009 mergedthe Verilog HDL Standard into the systemverilog Standard ,and officially ended the Verilog Standard . systemverilog -2009 Standard also added a number of additional featuresto the language (see [6] and [7]). 2009 was not the end of the evolution ofSystemVerilog.
5 Design size and complexity continues torapidly evolve. A design and verification language mustevolve to keep pace with designs. As soon as the IEEES ystemVerilog standards committee completedSystemVerilog-2009, work began on defining the nextgeneration of systemverilog , currently referred to as IEEEP1800- 2012 proposed systemverilog - 2012 [8]. Wish listsof new language features were developed, and from those a top 10 list of new features was created for categoriessuch as design modeling and testbench modeling. Furthermore, ambiguities in the SystemVerilogstandard, and occasional typographical errors, wereidentified as Electronic Design Automation (EDA)companies implemented systemverilog -2009 in varioustypes of software tools.
6 Along with specifying newlanguage features for the next generation ofSystemVerilog, the IEEE 1800 standards committee madea number of clarifications and minor corrections to work on specifying new features and clarificationfor systemverilog - 2012 was completed in December pre-ballot draft of the new Standard was prepared andreviewed during the month of January 2012 . At the timethis paper was written, a ballot draft was in the process ofbeing prepared, with the IEEE balloting process set tobegin in February 2012 and close in March data base used to track changes to theSystemVerilog Standard is called Mantis.
7 The Mantisdata base lists 162 changes for the proposedSystemVerilog- 2012 Standard . Of these 162 changes: 31 are new features that have been added toSystemVerilog. 60 are clarifications of how existing features in thestandard should behave. 71 are minor corrections to fonts, punctuation, etc. (plusa number of minor editorial corrections, such as fixing afont, that were not recorded in the data base).This focus of this paper is on the 31 new languagefeatures, and how those features can help make writingcomplex verification testbenches simpler or more NEW FEATURES IN systemverilog -2012A.
8 OOP enhancementsThree of the new features in the proposedSystemVerilog 2012 Standard affect Object OrientedProgramming (OOP). One is a convenience enhancementthat does not add new functionality. Another addsimportant functionality for helping OOP code avoid raceconditions with procedural code. The third enhancement issignificant a form of multiple Typed new() constructors (Mantis 3001)Previous versions of the systemverilog standardrequired that the type of an object to be constructed mustmatch the type of handle variable of that object s new()constructor.
9 Once constructed, a child handle can then beassigned to a handle of its parent type. To construct anobject and assign the handle to a parent type requires atleast three lines of code. For example:class base_trans; .. endclassclass reset_trans extends base_trans;.. endclassbase_trans t_base;reset_trans t_reset t_reset = new;t_base = t_reset;The typed new() constructor enhancement adds a classscope immediately before the new keyword, specifying theconstructed object s type independently of the assignmenttarget. This reduces the three lines of code above to asingle line:base_trans t_base = reset_trans::new;This new feature in systemverilog is a convenienceenhancement.
10 It does not add new functionality, but canhelp reduce the lines of code and make code more Nonblocking assignments to class properties (Mantis 2112) Previous versions of systemverilog did not allownonblocking assignments to class properties. The proposedSystemVerilog- 2012 Standard removes this base_trans;int data;bit resetN;endclassinitial beginresetN <= 0; // assert reset in NBA nonblocking assignments are primarily ahardware modeling construct used in RTL models, they arealso useful in verification code. Nonblocking assignmentsallow verification engineers a way to utilizeSystemVerilog s internal event scheduling regions tocontrol the order in which concurrent processes areevaluated.
