The IEEE Verilog 1364-2001 Standard; What's New and Why ...

1 The IEEE Verilog 1364-2001 StandardWhat's New, and Why You Need ItStuart SutherlandSutherland HDL, Inc.(presented at HDLCon in March 2000 minor updates made October, 2001) AbstractAt the time of this conference, the proposed IEEE 1364-2000 Verilog standard is complete, and in the ballotingprocess for final IEEE approval [update: official IEEE ratification was not completed until March 2001, makingthe official name IEEE 1364-2001 , and the nicknameVerilog-2001]. Verilog -2001 adds many significantenhancements to the Verilog language, which add greatersupport for configurable IP modeling, deep-submicronaccuracy, and design management. Other enhancementsmake Verilog easier to use. These changes will affecteveryone who uses the Verilog language, as well as thosewho implement Verilog software tools.

2 This paper presentsa summary of several of the enhancements in History of the IEEE 1364 Verilog standardThe Verilog Hardware Description Language was firstintroduced in 1984, as a proprietary language fromGateway Design Automation. The original Veriloglanguage was designed to be used with a single product,the Gateway Verilog -XL digital logic simulator. In 1989, Gateway Design Automation was acquired byCadence Design Systems. In 1990, Cadence released theVerilog Hardware Description Language and the VerilogProgramming Language Interface (PLI) to the publicdomain. Open Verilog International (OVI) was formed tocontrol the public domain Verilog , and to promote itsusage. Cadence turned over to OVI the FrameMakersource files of the Cadence Verilog -XL user s manual. Thisdocument became OVI s Verilog Reference 1993, OVI released its Verilog Reference Manual,which contained a few enhancements to the Veriloglanguage, such as array of instances.

3 OVI then submitted arequest to the IEEE to formally standardize Verilog IEEE formed a standards working group to create thestandard, and, in 1995, IEEE 1364-1995 became theofficial Verilog is important to note that for Verilog -1995, the IEEE standards working group did not consider anyenhancements to the Verilog language. The goal was tostandardize the Verilog language the way it was being usedat that time. The IEEE working group also decided not tocreate an entirely new document for the IEEE 1364standard. Instead, the OVI FrameMaker files were used tocreate the IEEE standard. Since the origin of the OVImanual was a user s manual, the IEEE 1364-1995 andIEEE 1364-2001 Verilog language reference manuals[1][2] are still organized somewhat like a user s Goals for IEEE 1364-2001 Verilog standardWork on the IEEE 1364-2001 Verilog standard began inJanuary 1997.

4 Three major goals were established: Enhance the Verilog language to help with today s deepsubmicron and intellectual property modeling issues. Ensure that all enhancements were both useful andpractical, and that simulator and synthesis vendorswould implement Verilog -2001 in their products. Correct any errata or ambiguities in the IEEE 1364-1995 Verilog Language Reference Manual. The Verilog -2001 standard working group was comprisedof about 20 participants, representing a diversified mix ofVerilog users, simulation vendors and synthesis working group was divided into three task forces: TheASIC Task Force developed enhancements to meet theneeds of very deep submicron timing accuracy. TheBehavioral Task Force developed enhancements forBehavioral and RTL modeling. The PLI Task Forceenhanced the Verilog Programming Language Interface tosupport changes from the other task forces, as well asadding new capabilities to the Modeling enhancementsThe 21 enhancements listed in this section give Verilogdesigners more capability for creating Verilog enhancements improve the ease and accuracy ofwriting synthesizable RTL models.

5 Other enhancementsallow models to be more scalable and re-usable. Onlychanges which add new functionality or syntax are listedhere. Clarifications to Verilog -1995 are not paper was first presented at the 9th Annual International HDL Conference and Exhibition, March 2000, Santa Clara, Minorupdates and clarifications were made by the author in October, 2001. Copyright 2000, Sutherland HDL, Inc., Tualatin, Oregon. 2000, Sutherland HDL, 2 of management Verilog configurationsThe Verilog -1995 standard leaves design management tosoftware tools, rather than making it part of the simulator vendor has devised ways to handledifferent versions of Verilog models, but these tool-specificmethods are not portable across all Verilog software adds configuration blocks, which allow theexact version and source location of each Verilog moduleto be specified as part of the Verilog language.

6 Forportability, virtual model libraries are used in configurationblocks, and separate library map files associate virtuallibraries with physical locations. Configuration blocks arespecified outside of module definitions. The names ofconfigurations exist in the same name space as modulenames and primitive names. New keywords config andendconfig are reserved in Verilog -2001. Additionalkeywords are reserved for use within a configurationblock: design, instance, cell, use and full syntax and usage of Verilog configuration blocksis beyond the scope of this paper. The following exampleillustrates a simple design configuration. The Verilogsource code is typical; a test bench module contains aninstance of the top-level of a design hierarchy, and the toplevel of the design includes instances of other test.

7 MyChip dut (..); /* instance of design */..endmodulemodule myChip(..);..adder a1 (..);adder a2 (..);..endmoduleThe configuration block specifies the source code locationof all, or specific, module instances. Because theconfiguration is specified outside of Verilog modules, theVerilog model source code does not need to be modified toreconfigure a design. In this configuration example,instance a1 of the adder will be compiled from the RTLlibrary, and instance a2 from a specific gate-level * define a name for this configuration */config cfg4/* specify where to find top level modules */design * set the default search order for findinginstantiated modules */default liblist rtlLib gateLib;/* explicitly specify which library to usefor the following module instance */instance liblist gateLib;endconfigThe configuration block uses virtual libraries to specify thelocation of the Verilog model sources.

8 A library map file isused to associate the virtual library names with physicalfile locations. For example:/* location of RTL models (current directory) */library rtlLib ./*.v;/* Location of synthesized models */library gateLib ./synth_out/*.v; models Verilog generateThe Verilog -1995 standard has limitations on definingVerilog models that are scalable and easy to re-use in otherdesigns. Verilog -1995 has the array of instances construct,which, though powerful, does not provide the flexibilityneeded for truly scalable, complex design adds generate loops, which permitgenerating multiple instances of modules and primitives, aswell as generating multiple occurrences of variables, nets,tasks, functions, continuous assignments, initialprocedures, and always procedures. Generated declarationsand instantiations can be conditionally created, using if else decisions and case statements.

9 Four new keywords have been added in Verilog -2001:generate, endgenerate, genvar and localparam. Thegenvar keyword is a new data type, which stores positiveinteger values. It differs from other Verilog variables inthat it can be assigned values and changed during compileor elaboration time. The index variable used in a generateloop must be declared as a genvar. A localparam is aconstant that is similar to a parameter, but which cannot bedirectly changed using parameter redefinition. A generateblock can also use certain Verilog programming statementsto control what objects are generated. These are: for loops,if else decisions and case following example illustrates using generate to createscalable module instances for a multiplier. If either of themultiplier s a_width or b_width parameters are less than 8,a CLA multiplier is instantiated.

10 If a_width and b_widthare 8 bits or more, a Wallace tree multiplier is multiplier (a, b, product);parameter a_width = 8, b_width = 8;localparamproduct_width = a_width+b_width;input [a_width-1:0] a;input [b_width-1:0] b;output[product_width-1:0]product;gener ateif((a_width < 8) || (b_width < 8))CLA_multiplier #(a_width, b_width)u1 (a, b, product);elseWALLACE_multiplier #(a_width, b_width)u1 (a, b, product);endgenerateendmodule 2000, Sutherland HDL, 3 of 8 The next example illustrates a multi-bit wide adder whichuses a generate for-loop to instantiate both the primitiveinstances and the internal nets connecting the primitives. Are-definable parameter constant is used to set the width ofthe multi-bit adder and the number of instances Nbit_adder (co, sum, a, b, ci);parameter SIZE = 4;output [SIZE-1:0] sum;output co;input [SIZE-1:0] a, b;input ci;wire [SIZE:0] c;genvar i;assign c[0] = ci;assign co = c[SIZE];generatefor(i=0; i<SIZE; i=i+1)begin:addbitwire n1,n2,n3; //internal netsxor g1 ( n1, a[i], b[i]);xor g2 (sum[i],n1, c[i]);and g3 ( n2, a[i], b[i]);and g4 ( n3, n1, c[i]);or g5 (c[i+1],n2, n3);endendgenerateendmoduleIn the preceding example, each generated net will have aunique name, and each generated primitive instance willhave a unique instance name.