Transcription of VCU118 Evaluation Board - Xilinx
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VCU118 Evaluation Board - Xilinx
VCU118 Evaluation BoardUser GuideUG1224 ( ) October 17, 2018 VCU118 Board User Guide2UG1224 ( ) October 17, HistoryThe following table shows the revision history for this the PCI Express endpoint connectivity list. Added the Electrostatic Discharge Caution section. Updated Callout 25 in Table 2-1. Updated SW16 in Table 2-2. Updated Jumper J7 in Table 2-3. Added Note 1 to Table 2-4. Updated the switch positions in Figure 2-4. Updated the Virtex UltraScale+ XCVU9P-L2 FLGA2104 Device, DDR4 Component Memory, RLD3 Component Memory, and PCI Express Endpoint Connectivity descriptions. Updated the callout locations in the User I/O and CPU Reset Pushbutton sections. Updated the 4-pole DIP SW12 devices in Table 3-29. Revised Note 1 in Table 3-33. Updated the switch positions in Figure Appendix B, updated the Overview and deleted the VCU118 Board Constraints File Listing section. Updated Appendix D, Regulatory and Compliance new information below Figure 2-4 and Table 3-25. Revised Table 3-24 notes.
VCU118 Board User Guide 6 UG1224 (v1.4) October 17, 2018 www.xilinx.com Chapter 1 Introduction Overview The VCU118 evaluation board for the Xilinx® Virtex® UltraScale+™ FPGA provides a hardware environment for developing and …
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