Transcription of Verilator - Veripool
{{id}} {{{paragraph}}}
Example: air traffic controller
Verilator - Veripool
Verilator Release Wilson Snyder 2022-01-19. GETTING STARTED. 1 Overview 1. 2 Examples 2. Example C++ Execution .. 2. Example systemc Execution .. 3. Examples in the Distribution .. 4. 3 Installation 6. Package Manager Quick Install .. 6. Git Quick Install .. 6. Detailed Build Instructions .. 7. Verilator Build Docker Container .. 10. Verilator Executable Docker Container .. 11. 4 Verilating 13. C++ and systemc Generation .. 13. Hierarchical Verilation .. 14. Cross Compilation .. 15. Multithreading .. 15. GNU Make .. 17. CMake .. 17. 5 Connecting to Verilated Models 20. Structure of the Verilated Model .. 20. Connecting to C++ .. 21. Connecting to systemc .. 22. Direct Programming Interface (DPI) .. 22. Verification Procedural Interface (VPI) .. 25. Wrappers and Model Evaluation Loop .. 26. Verilated and VerilatedContext .. 27. 6 Simulating (Verilated-Model Runtime) 28. Benchmarking & Optimization .. 28. Coverage Analysis .. 29. Code Profiling .. 31. Thread Profiling .. 31.
CHAPTER ONE OVERVIEW Welcome to Verilator! The Verilator package converts Verilog1 and SystemVerilog2 hardware description language (HDL) designs into a C++ or SystemC model that after compiling can be executed. Verilator is not a traditional simulator, but a compiler.
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: