A Cloud-Scale Acceleration Architecture
Altera Stratix V D5 FPGA. 256 Mb Config Flash. U S B. 4 GB DDR3 -1600. 40Gb QSFP Network to TOR. USB to JTAG µC. to NIC. 4 lanes @ 10.3125 Gbps. 4 lanes @ 10.3125 Gbps. 72 bits QSPI (with ECC) PCIe Mezanine Connector. PCIe Gen3 x8. PCIe Gen3 x8. Temp, power, LEDs. I2C. Fig. 2. Block diagram of the major components of the accelerator board. of ...
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